In this work, a multifunctional drain-engineered (DE) vertically stacked (VS) junctionless (JL) FET exhibiting device reconfigurability and its application as an inverter are proposed and simulated. The proposed DE VS JL FET consists of stacked \({n}^{+}\) and \({p}^{+}\) device layers having SiO\(_{2}\) isolation vertically, with n-drain (\({D}_n\)) and p-drain (\({D}_p\)) silicide regions connected together. Highly doped device layers allow for the formation of a thin-dopant segregation layer on the drain side. To mimic the realistic channel/drain junctions, silicides with realistic Schottky-barrier heights are chosen (\({D}_n\): \(\hbox {ErSi}_x\) \(\approx \) 0.28 eV and \({D}_p\): PtSi \(\approx \) 0.24 eV). Both device layers contribute individually to the n-FET and p-FET complementary operation when biased adequately. Moreover, the transient analysis shows that the device in the inverter mode performs reasonably well even when the \({V}_{\text {DD}}\) is scaled up to 0.5 V. Furthermore, a 3-transistor-based 2-input XOR gate standard cell has also been realized using the proposed device.

在这项工作中，提出并模拟了一种具有器件可重构性的多功能漏极工程（DE）垂直堆叠（VS）无结（JL）FET及其在逆变器中的应用。所提出的DE VS JL FET由堆叠的\（{N} ^ {+} \）和\（{P} ^ {+} \）具有的SiO器件层\（_ {2} \）隔离垂直，与Ñ -漏极（\（{D} _n \））和p-漏极（\（{D} _p \））硅化物区域连接在一起。高度掺杂的器件层允许在漏极侧形成薄掺杂剂隔离层。为了模拟实际的沟道/漏极结，选择了具有实际肖特基势垒高度的硅化物（\（{D} _n \）：\（\ hbox {ErSi} _x \） \（\ approx \） 0.28 eV和\（{D} _p \）：PtSi \（\ approx \） 0.24 eV）。当充分偏置时，两个器件层都分别有助于n -FET和p -FET互补操作。此外，瞬态分析表明，即使将\（{V} _ {\ text {DD}} \）缩放至0.5 V，逆变器模式下的设备性能仍相当好。此外，基于3晶体管的2输入的异或门标准单元也已使用该器件实现。