This paper introduces FPGA-based implementation of Modular Multiplier based on Montgomery Modular Multiplier (MMM) architecture. The proposed design is a modification in the structure of MMM without any multiplication or subtraction processes. The pre-computation addition of the modulus and multiplicand has enhanced the maximum frequency of the design on FPGA. The new modification has improved the performance and reduced the area of the MMM hardware module. A Xilinx Virtex-6 FPGA implementation of the proposed architecture occupies 908 LUT and 1318 LUT for 256-bit and 512-bit modular multiplications for any modulus respectively. Comparing with other related designs our design occupies the smallest area, and has a better efficiency. The proposed design has enhanced the efficiency in the range between 1.41 to 8.7 times the efficiency of other relevant designs. The proposed design is intended for hardware applications of lightweight cryptographic modules that is utilized for the System on Chip (SoC) and Internet of Things (IoT) devices.

本文介绍了基于蒙哥马利模块化乘法器（MMM）架构的基于FPGA的模块化乘法器的实现。提出的设计是对MMM结构的修改，没有任何乘法或减法过程。模数和被乘数的预计算相加提高了FPGA设计的最大频率。新修改改进了性能，并减小了MMM硬件模块的面积。所提出架构的Xilinx Virtex-6 FPGA实现分别针对任何模数的256位和512位模乘占用908 LUT和1318 LUT。与其他相关设计相比，我们的设计占地面积最小，效率更高。拟议的设计提高了效率，范围为1.41至8。效率是其他相关设计的7倍。拟议的设计旨在用于轻量级密码模块的硬件应用，该模块用于片上系统（SoC）和物联网（IoT）设备。