This paper presents a low jitter multiplying delay-locked loop (MDLL) with static phase offset elimination (SPOE) applied to time-to-digital converter (TDC). To reduce static phase offset (SPO) between the reference clock and the output feedback clock, a SPOE techniques based on time amplifier (TA) is proposed, which the reference clock can be accurately injected for timing or phase calibration. The logic selector (LS) used a simplified form to complete mode switching with faster response times. The improved phase detector (PD) implements direct phase discrimination between the output feedback clock and the reference clock. The improved voltage-controlled delay line (VCDL) also makes the MDLL implementing a uniform split-phase output characteristic. The test chip is designed and fabricated in TSMC 0.35-μm 3.3 ​V complementary metal-oxide-semiconductor (CMOS) process which occupies a core area of 0.26 ​mm². The measurement results show that the output clock jitters at 320 ​MHz frequency is 3.17 ps for root mean square, with the multiplication ratio of 8. The circuit has eight split-phase output clocks with a uniform separation within 45° ​± ​3.4°.

本文提出了一种适用于时间数字转换器（TDC）的具有静态相位偏移消除（SPOE）的低抖动乘法延迟锁定环（MDLL）。为了减少参考时钟和输出反馈时钟之间的静态相位偏移（SPO），提出了一种基于时间放大器（TA）的SPOE技术，可以将参考时钟准确地注入以进行定时或相位校准。逻辑选择器（LS）使用简化的形式以更快的响应时间完成模式切换。改进的鉴相器（PD）实现了输出反馈时钟和参考时钟之间的直接相位区分。改进的压控延迟线（VCDL）也使MDLL实现了统一的分相输出特性。测试芯片是在台积电0.35-μm3。²。测量结果表明，在320 MHz频率下，均方根的输出时钟抖动为3.17 ps，乘数比为8.该电路具有八个分相输出时钟，它们在45°±3.4°内均匀间隔。