Addition is the key operation in digital systems, and floating-point adder (FPA) is frequently used for real number addition because floating-point representation provides a large dynamic range. Most of the existing FPA designs are synchronous and their activities are coordinated by clock signal(s). However, technology scaling has imposed several challenges like clock skew, clock distribution, etc., on synchronous design due to presence of clock signal(s). Asynchronous design is an alternate approach to eliminate these challenges imposed by the clock, as it replaces the global clock with handshaking signals and utilizes a communication protocol to indicate the completion of activities. Bundled data and dual-rail coding are the most common communication protocols used in asynchronous design. All existing asynchronous floating-point adder (AFPA) designs utilize dual-rail coding for completion detection, as it allows the circuit to acknowledge as soon as the computation is done; while bundled data and synchronous designs utilizing single-rail encoding will have to wait for the worst-case delay irrespective of the actual completion time. This paper reviews all the existing AFPA designs and examines the effects of the selected communication protocol on its performance. It also discusses the probable outcome of AFPA designed using protocols other than dual-rail coding.

中文翻译：

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异步浮点加法器和通信协议：一项调查

加法是数字系统中的关键操作，并且浮点加法器（FPA）经常用于实数加法，因为浮点表示法提供了较大的动态范围。现有的大多数FPA设计都是同步的，其活动由时钟信号进行协调。然而，由于时钟信号的存在，技术缩放对同步设计提出了一些挑战，例如时钟偏斜，时钟分配等。异步设计是消除时钟带来的这些挑战的一种替代方法，因为它用握手信号代替了全局时钟，并利用通信协议来指示活动的完成。捆绑数据和双轨编码是异步设计中最常用的通信协议。所有现有的异步浮点加法器（AFPA）设计都使用双轨编码进行完成检测，因为它允许电路在计算完成后立即确认。而采用单轨编码的捆绑数据和同步设计将不得不等待最坏情况下的延迟，而与实际完成时间无关。本文回顾了所有现有的AFPA设计，并研究了所选通信协议对其性能的影响。它还讨论了使用双轨编码以外的协议设计的AFPA的可能结果。而采用单轨编码的捆绑数据和同步设计将不得不等待最坏情况下的延迟，而与实际完成时间无关。本文回顾了所有现有的AFPA设计，并研究了所选通信协议对其性能的影响。它还讨论了使用双轨编码以外的协议设计的AFPA的可能结果。而采用单轨编码的捆绑数据和同步设计将不得不等待最坏情况下的延迟，而与实际完成时间无关。本文回顾了所有现有的AFPA设计，并研究了所选通信协议对其性能的影响。它还讨论了使用双轨编码以外的协议设计的AFPA的可能结果。