Chemical vapor deposition (CVD) and chemical-mechanical planarization (CMP) of tungsten have been the enabling process technologies for semiconductor manufacturing. Despite the long history and relative maturity, however, their combined effects on the electrical performance and topographic variation of W metallization are scarcely reported in the open literature. A previous work on Cu plating demonstrates the feasibility of reducing topography and improving electrical resistance uniformity by manipulating Cu plating process for superior incoming filling across different patterns and line widths within the die. Adopting the similar concept, this study utilizes SiH 4 and WF 6 gas chemistry in a CVD-W process optimized for reduced seam formation. 300 mm wafers with varying W overburden thickness are deposited and polished in order to examine the impacts on resulting resistance uniformity across different line widths, and within-die topography. It will be demonst...

中文翻译：

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钨金属化过程中CVD和CMP的工艺优化

钨的化学气相沉积（CVD）和化学机械平坦化（CMP）已经成为半导体制造的使能工艺技术。尽管历史悠久且相对成熟，但是在公开文献中几乎没有报道它们对钨金属化的电性能和形貌变化的综合影响。先前进行的铜镀层工作证明了通过控制铜镀层工艺以实现跨模具内不同图案和线宽的优异进料填充的方法，可以减小形貌并提高电阻均匀性。通过采用类似的概念，本研究在针对减少接缝形成而优化的CVD-W工艺中利用了SiH 4和WF 6气体化学。沉积并抛光300毫米宽W覆盖层厚度的晶片，以检查其对不同线宽和晶粒内形貌对电阻均匀性的影响。这将是示威...