Delay circuits are one of the key components in time domain blocks such as pulse width modulator. This work describes the working of a differential delay circuit under process, voltage and temperature. The proposed design is also coupled to a typical power delivery network (PDN) and a central processing unit (CPU) core ramping current from 0 A to 10–40A in 10 ns Simulated in a 90-nm CMOS technology and power supply voltage (Vdd) of 1.1 V, the post-layout delay was noted to be 227 ps During this time, differential signals at the input are switching at 1GHz while the rise, fall times are about 0.1ns The power thus dissipated corresponds to 235 μW. But, delay changes by about 0.4–0.9 ps at every process corner while temperature increases by 1^OC. The corresponding variation for 1mV drop in power supply voltage is 0.1–0.4ps In addition to that, a change in temperature enables the average power to fluctuate between 192.8 and 264μW, whereas, 0.6μW for 1mV drop in power supply voltage. The study of 500 runs Monte-Carlo analysis for a NN process indicates an almost identical behavior with the no skew data in post-layout. The rms jitter is within 0.01–0.3ps while the delay per mV change in power supply is 0.21 ps/mV. But a sudden current drawn by the CPU causes the voltage V_P close to the die to oscillate. This enables the delay to vary than those obtained with zero power supply noise. The sudden current also introduces jitter in the output swing. The jitter so induced varies linearly with the AC first droop.

延迟电路是时域模块（例如脉冲宽度调制器）中的关键组件之一。这项工作描述了差分延迟电路在过程，电压和温度下的工作。拟议的设计还与典型的供电网络（PDN）和中央处理器（CPU）内核在10 ns内从0 A到10-40A的斜坡电流耦合，并在90nm CMOS技术和电源电压（Vdd）下进行了仿真。 1.1的V），后布局德拉ý人们注意到，227个PS在此期间，在输入差分信号为1GHz而上升，下降时间为约0.1ns从而耗散对应于235μW的功率开关。但是，当温度每升高1 ^O时，延迟在每个工艺角变化约0.4–0.9 ps。C.电源电压下降1mV的相应变化为0.1-0.4ps。此外，温度变化可使平均功率在192.8和264μW之间波动，而电源电压下降1mV的变化为0.6μW。对NN过程进行500次蒙特卡洛分析的研究表明，布局几乎没有偏差，其行为几乎相同。均方根抖动在0.01-0.3ps之内，而电源每mV变化的延迟为0.21 ps / mV。但是CPU突然吸收电流会导致靠近芯片的电压V _P振荡。与零电源噪声所获得的延迟相比，这可使延迟发生变化。突然的电流还会在输出摆幅中引入抖动。如此引起的抖动随交流第一下降而线性变化。