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Two-step write-verify scheme and impact of the read noise in multilevel RRAM based inference engine
Semiconductor Science and Technology ( IF 1.9 ) Pub Date : 2020-10-10 , DOI: 10.1088/1361-6641/abb842
Wonbo Shim 1 , Jae-sun Seo 2 , Shimeng Yu 1
Affiliation  

The accuracte cell conductance tuning is critical to realizing multilevel resistive random access memory (RRAM) based compute-in-memory inference engine. To tighten the distribution of the cells of each state, we developed a two-step write-verify scheme within the limited number of iteration, which was tested on a test vehicle based on HfO2 RRAM array to realize 2-bit per cell. The conductance of the cells are gathered in the targeted range within 10 loops of set and reset process for each step. Moreover, the read noise of the RRAM cells is statistically measured and its impact on the upper-bound of analog-to-digital converter (ADC) resolution is predicted. The result shows that the intemediate state cells under relatively high read voltage (e.g. 0.2V) are vulnerable to the read noise. Fortunately, the aggregated read noise along the column will not disturb the output of a 5-bit ADC that is required for 128×128 array with 2-bit per cell.

中文翻译:

基于多级 RRAM 的推理引擎中的两步写验证方案和读噪声的影响

精确的单元电导调整对于实现基于多级电阻随机存取存储器 (RRAM) 的内存计算推理引擎至关重要。为了加强每个状态单元的分布,我们在有限的迭代次数内开发了一个两步写验证方案,该方案在基于 HfO2 RRAM 阵列的测试车辆上进行了测试,以实现每单元 2 位。在每个步骤的 10 个设置和重置过程循环内,细胞的电导被收集在目标范围内。此外,对 RRAM 单元的读取噪声进行统计测量,并预测其对模数转换器 (ADC) 分辨率上限的影响。结果表明,处于较高读取电压(例如0.2V)的中间状态单元容易受到读取噪声的影响。幸运的是,
更新日期:2020-10-10
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