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A novel approach to fractional-N PLLs generating ultra-fast low-noise chirps for FMCW radar
Integration ( IF 1.9 ) Pub Date : 2020-10-11 , DOI: 10.1016/j.vlsi.2020.09.009
Frank Herzel , Arzu Ergintav , Gunter Fischer

This paper presents a novel approach to generate ultra-fast chirps for frequency-modulated continuous wave (FMCW) radar systems. A symmetric triangular frequency chirp is analyzed. A very large loop bandwidth could minimize the PLL settling time, but would result in a high phase noise and in large spurs. This work minimizes the settling times without using an excessive loop bandwidth. Rather, the initial condition of the dynamic phase error after the turn-around points (TAPs) is minimized by switching the reference phase in conjunction with one of the two methods: Firstly, a well-defined offset current is added to the charge pump output current, and its sign is switched at the TAPs. Secondly, a binary weighted loop filter capacitor array is used in the loop filter, and the total capacitance is adapted to the slope of the frequency sweep. While the first method lends itself to a fully integrated PLL design including the loop filter, the second method achieves a lower in-band phase noise.



中文翻译:

小数N分频PLL的新颖方法可为FMCW雷达生成超快速低噪声chi

本文提出了一种新颖的方法来为调频连续波(FMCW)雷达系统生成超快线性调频脉冲。分析了一个对称的三角频率rp。很大的环路带宽可以最小化PLL的建立时间,但会导致高相位噪声和大杂散。这项工作可以在不使用过多环路带宽的情况下将建立时间降至最低。相反,通过结合以下两种方法之一来切换参考相位,可以最大程度地减小转折点(TAP)之后动态相位误差的初始条件:首先,将明确定义的失调电流添加到电荷泵输出中电流,其符号在TAP处切换。其次,在环路滤波器中使用二进制加权环路滤波器电容器阵列,并且总电容适应于频率扫描的斜率。

更新日期:2020-10-30
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