Recently, the increasing need to run applications for significant data analytics, and the augmented demand of useful tools for big data computing systems has resulted in a cumulative necessity for efficient platforms with high performance and realizable power consumption, for example, chip multiprocessors (CMPs). Correspondingly, due to the demand for features like shrinkable sizes, and the concurrent need to pack increasing numbers of transistors into a single chip, has led to serious design challenges, consuming a significant of power within high area densities. We present a reconfigurable hybrid cache system for last level cache (LLC) by the integration of emerging designs, such as STT-RAM with SRAM memories. This approach consists of two phases: off- time and on-time. In off time, training NN is implemented while in the on-time phase, a reconfiguration cache uses a neural network (NN) learning approach to predict demanded latency of the running application. Experimental results of a three-dimensional chip with 64 cores show that the suggested design under PARSEC benchmarks provides a speedup in terms of the performance at 25% and improves energy consumption by 78.4% in comparison to non-reconfigurable pure SRAM cache architectures.

近来，运行用于大量数据分析的应用程序的需求不断增长，以及对大数据计算系统的有用工具的需求不断增长，导致对具有高性能和可实现功耗的高效平台（例如，芯片多处理器（CMP））的累积需求。相应地，由于对诸如可缩小尺寸的特征的需求，以及同时需要将越来越多的晶体管封装到单个芯片中，导致了严重的设计挑战，在高面积密度内消耗了大量功率。通过集成新兴设计（例如带有SRAM存储器的STT-RAM），我们提出了一种用于最后一级缓存（LLC）的可重新配置的混合缓存系统。该方法包括两个阶段：关闭时间和打开时间。在非工作时间，在准时阶段实施训练NN，重新配置缓存使用神经网络（NN）学习方法来预测正在运行的应用程序所需的延迟。具有64个内核的三维芯片的实验结果表明，与不可重新配置的纯SRAM缓存体系结构相比，在PARSEC基准下建议的设计可将性能提高25％，并将能耗降低78.4％。