Emerging three-dimensional (3D) memory technologies, such as the Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM), provide high-bandwidth and massive memory-level parallelism. With the growing heterogeneity and complexity of computer systems (CPU cores and accelerators, etc.), efficiently integrating emerging memories into existing systems poses new challenges and requires detailed evaluation in a realistic computing environment. In this article, we propose MEG, an open source, configurable, cycle-exact, and RISC-V-based full-system emulation infrastructure using FPGA and HBM. MEG provides a highly modular hardware design and includes a bootable Linux image for a realistic software flow, so that users can perform cross-layer software-hardware co-optimization in a full-system environment. To improve the observability and debuggability of the system, MEG also provides a flexible performance monitoring scheme to guide the performance optimization. The proposed MEG infrastructure can potentially benefit broad communities across computer architecture, system software, and application software. Leveraging MEG, we present two cross-layer system optimizations as illustrative cases to demonstrate the usability of MEG. In the first case study, we present a reconfigurable memory controller to improve the address mapping of standard memory controller. This reconfigurable memory controller along with its OS support allows us to optimize the address mapping scheme to fully exploit the massive parallelism provided by the emerging three-dimensional (3D) memories. In the second case study, we present a lightweight IOMMU design to tackle the unique challenges brought by 3D memory in providing virtual memory support for near-memory accelerators. We provide a prototype implementation of MEG on a Xilinx VU37P FPGA and demonstrate its capability, fidelity, and flexibility on real-world benchmark applications. We hope MEG fills a gap in the space of publicly available FPGA-based full-system emulation infrastructures, specifically targeting memory systems, and inspires further collaborative software/hardware innovations.

中文翻译：

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乙二醇

新兴的三维 (3D) 内存技术，例如混合内存立方体 (HMC) 和高带宽内存 (HBM)，可提供高带宽和海量内存级别的并行性。随着计算机系统（CPU 内核和加速器等）的异构性和复杂性日益增加，将新兴存储器有效地集成到现有系统中提出了新的挑战，需要在现实的计算环境中进行详细评估。在本文中，我们提出了 MEG，这是一个使用 FPGA 和 HBM 的开源、可配置、周期精确和基于 RISC-V 的全系统仿真基础设施。MEG 提供高度模块化的硬件设计，并包含一个可启动的 Linux 映像以实现真实的软件流程，以便用户可以在全系统环境中执行跨层软硬件协同优化。为了提高系统的可观察性和可调试性，MEG还提供了灵活的性能监控方案来指导性能优化。拟议的 MEG 基础设施可能使计算机体系结构、系统软件和应用软件的广泛社区受益。利用 MEG，我们提出了两个跨层系统优化作为说明性案例来展示 MEG 的可用性。在第一个案例研究中，我们提出了一种可重新配置的内存控制器来改进标准内存控制器的地址映射。这种可重新配置的内存控制器及其操作系统支持使我们能够优化地址映射方案，以充分利用新兴的三维 (3D) 内存提供的大规模并行性。在第二个案例研究中，我们提出了一种轻量级 IOMMU 设计，以应对 3D 内存在为近内存加速器提供虚拟内存支持方面带来的独特挑战。我们在 Xilinx VU37P FPGA 上提供 MEG 的原型实现，并在实际基准应用中展示其功能、保真度和灵活性。我们希望 MEG 填补公开可用的基于 FPGA 的全系统仿真基础设施领域的空白，特别针对内存系统，并激发进一步的协作软件/硬件创新。