This article presents a low-power 1/4-rate four-level pulse amplitude modulation (PAM4) receiver with an adaptive variable-gain rectifier (AVGR)-based decoder in 28-nm CMOS technology. The PAM4 input signal is preconditioned by a continuous-time linear equalizer (CTLE) then sampled into four branches of decoders by 1/4-rate clocks. The proposed AVGR-based PAM4-to-nonreturn-to-zero (NRZ) decoder performs gain adaptation and amplitude rectification simultaneously for decoding the least significant bit (LSB). The linear sense amplifier in the AVGR is modified from a latch to achieve a high gain and low power. Compared with the full-rate receiver adopting a decoder consisting of three comparators, this design achieves a better power efficiency by employing a 1/4-rate topology and merging a variable-gain function into the decoder. Experimental results demonstrate that the receiver chip can receive and decode a 24-Gb/s 190-mVpp PAM4 signal at a BER of 10−11 and a bit efficiency of 1.38 pJ/bit.

中文翻译：

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具有基于自适应可变增益整流器的解码器的低功耗 PAM4 接收器

本文介绍了一种低功耗 1/4 速率四电平脉冲幅度调制 (PAM4) 接收器，该接收器具有采用 28 纳米 CMOS 技术的基于自适应可变增益整流器 (AVGR) 的解码器。PAM4 输入信号由连续时间线性均衡器 (CTLE) 进行预处理，然后通过 1/4 速率时钟采样到解码器的四个分支。所提出的基于 AVGR 的 PAM4 到不归零 (NRZ) 解码器同时执行增益自适应和幅度整流以解码最低有效位 (LSB)。AVGR 中的线性读出放大器由锁存器修改而来，以实现高增益和低功耗。与采用由三个比较器组成的解码器的全速率接收器相比，该设计通过采用 1/4 速率拓扑并将可变增益函数合并到解码器中，实现了更好的功率效率。