Decreasing Drain‐Induced‐Barrier‐Lowering (DIBL) is one of the nondesirable short‐channel effects, causes the threshold voltage of the transistor to be reduced by increasing the drain voltage. DIBL makes it impossible for engineers to consider V_T as a constant, and it is necessary to calculate V_T as a function of the drain voltage. Therefore, to consider the DIBL effect in the design of ICs, a large computational burden is imposed on the system, which slows down the simulation process in circuit‐level simulators. Accordingly, a Nonlinear Feed‐Forward Memory‐Less (NFFML) model using the Gram‐Schmidt orthogonalization approach is proposed, which calculates the V_T of the new generation of MOSFETs, that is, Junctionless Double‐Gate MOSFETs (JL‐DG‐MOSFETs), with high precision and a significant speed‐up in the computation of the model. It is shown that the proposed numerical method is 313 times faster than the state‐of‐the‐art analytical model. The normalized MSE is 0.435% on average, showing that the proposed approach can be a fast and accurate candidate for replacing the analytical modeling.

中文翻译：

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非线性前馈无记忆模型可快速预测无结双栅极MOSFET中的阈值电压

减少漏极感应势垒降低（DIBL）是不希望的短沟道效应之一，它会通过增加漏极电压来降低晶体管的阈值电压。DIBL使工程师无法将V _T视为常数，因此有必要将V _T计算为漏极电压的函数。因此，要考虑IC设计中的DIBL效应，系统将承受较大的计算负担，这会减慢电路级仿真器的仿真过程。因此，提出了使用Gram-Schmidt正交化方法的非线性前馈记忆减少（NFFML）模型，该模型可计算V _T新一代MOSFET的一种，即无结双栅极MOSFET（JL-DG-MOSFET），在模型计算中具有很高的精度和明显的加速性。结果表明，所提出的数值方法比最新的分析模型快313倍。标准化的MSE平均为0.435％，这表明所提出的方法可以快速，准确地替代分析模型。