Schottky-barrier field-effect transistors (SBF-ETs) based on 2-D semiconductors had been investigated as a substitute for a conventional metal–oxide–semiconductor field-effect transistor (MOSFET) based on bulk silicon in the field of high-performance (HP) device. Especially, the monolayer SiC has been studied because it has a large band gap, which results in reducing the short-channel effect. In this article, the gate–source/drain underlap-dependent characteristics of HP SBFETs based on monolayer SiC with 5.1- and 4.6-nm gate lengths are investigated through ab initio simulations. The performances of the 5.1-nm monolayer SiC SBFET are degraded by the gate–source/drain underlap. The gate–source/drain underlap, however, shows the different improved performances for the 4.6-nm monolayer SiC SBFET. The gate–source underlap could enhance the ON-current to $2792~\mu \text{A}/\mu \text{m}$ and the gate–drain underlap can enhance the ON-current to $1754~\mu \text{A}/\mu \text{m}$ , which all far exceed the International Technology Roadmap for Semiconductors (ITRS) requirement.

中文翻译：

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栅源/漏重叠对单层碳化硅肖特基势垒场效应晶体管性能的影响

基于二维半导体的肖特基势垒场效应晶体管 (SBF-ET) 已被研究作为高性能领域中基于体硅的传统金属氧化物半导体场效应晶体管 (MOSFET) 的替代品。 (HP) 设备。尤其是单层碳化硅，由于其带隙大，减少了短沟道效应，因此得到了研究。在本文中，基于栅极长度为 5.1 和 4.6 纳米的单层 SiC 的 HP SBFET 的栅极-源极/漏极下重叠相关特性通过从头开始模拟。5.1-nm 单层 SiC SBFET 的性能因栅源/漏底重叠而降低。然而，栅极-源极/漏极重叠显示了 4.6 nm 单层 SiC SBFET 的不同改进性能。栅源重叠可以将导通电流提高到 $2792~\mu\text{A}/\mu\text{m}$ 和栅漏重叠可以提高导通电流 $1754~\mu\text{A}/\mu\text{m}$ ，这些都远远超过了国际半导体技术路线图 (ITRS) 的要求。