In this article, we present an appropriate compact model of spacer (SP) region for static characteristics of 3-D NAND flash memories. Though many studies on 3-D NAND flash have focused on the intrinsic part, they have not considered analysis on the SP region with gate-surrounded structure which is inevitable for 3-D NAND flash string due to punch-and-plug process. We focus on the electrostatics on the SP region of the 3-D NAND flash and suggest a concept of bias ratio (BR) which can evaluate the average influence of fringing electric field on the parasitic part for efficient implantation to the compact model. First, we introduce the modeling method of the SP region and then verify our modeling results by comparing channel potential using 3-D technology computer-aided design (TCAD) simulation. We also investigate the BR dependences on various device dimensions, and the dependences are comparable with the trends of outer-fringing capacitance. Finally, we demonstrate that our compact model can be efficiently applied to circuit simulation for various bias conditions and varying dimensions such as tapered channel structure, without the necessity of additional parameter extractions for each dimension.

中文翻译：

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3-D nand Flash Memory静态特性的间隔区SPICE紧凑模型研究

在本文中，我们针对 3-D NAND 闪存的静态特性提出了一个合适的间隔区 (SP) 紧凑模型。虽然许多关于 3-D NAND 闪存的研究都集中在本征部分，但他们没有考虑对具有栅极环绕结构的 SP 区域进行分析，这对于 3-D NAND 闪存串来说是不可避免的，因为打孔和插拔工艺。我们专注于 3-D NAND 闪存 SP 区域的静电，并提出偏置比 (BR) 的概念，该概念可以评估边缘电场对寄生部分的平均影响，以便有效植入紧凑模型。首先，我们介绍了 SP 区域的建模方法，然后通过使用 3-D 技术计算机辅助设计 (TCAD) 模拟比较通道电位来验证我们的建模结果。我们还研究了 BR 对各种器件尺寸的依赖性，这种依赖性与外边缘电容的趋势相当。最后，我们证明了我们的紧凑模型可以有效地应用于各种偏置条件和不同维度（例如锥形通道结构）的电路仿真，而无需为每个维度提取额外的参数。