The timing properties of asynchronous circuits can be summarized using cyclic graphs that capture max-delay constraints between signal transitions. There are many results on the timing analysis problem, but they all make various simplifying assumptions on the connectivity properties of the underlying timing graph. Most results provide approximate timing characteristics, with a few providing exact results on the circuit’s timing behavior. In this article, we provide results that exactly characterize the timing properties for a more general class of max-delay constraints. We show that the circuit can be partitioned into regions with different periodicities, and provide an efficient algorithm to compute all the periods of the system.

中文翻译：

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多周期异步电路的精确时序分析

异步电路的时序特性可以使用捕捉信号转换之间最大延迟约束的循环图来概括。关于时序分析问题有很多结果，但它们都对底层时序图的连通性属性做出了各种简化假设。大多数结果提供近似的时序特性，少数结果提供电路时序行为的准确结果。在本文中，我们提供的结果可以准确表征更一般的最大延迟约束类别的时序属性。我们表明电路可以划分为具有不同周期的区域，并提供一种有效的算法来计算系统的所有周期。