In this article, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is proposed based on a charge-based model. In particular, we have investigated the effect of the thickness of the ferroelectric on the I-V characteristics. Importantly, our model predicts that the negative capacitance minimizes short channel effects and enhances current overdrive, enabling both low power operation and more efficient transistor size scaling, while the effect on reducing subthreshold slope shows systematic improvement, with subthermionic subthreshold slope values at high current levels. Our predictive results in a long channel junctionless with NC show an improvement in ON current by a factor of 6 in comparison to junctionless FET. The set of equations can be used as a basis to explore how such a technology booster and its scaling will impact the main figures of merit of the device in terms of power performances and gives a clear understanding of the device physics. The validity of the analytical model is confirmed by extensive comparisons with numerical TCAD simulations in all regions of operation, from deep depletion to accumulation and from linear to saturation.

中文翻译：

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负电容双栅极无结 FET：摆动、过驱动和短沟道效应的基于电荷的建模研究

在本文中，基于电荷模型提出了对称长沟道双栅无结晶体管中负电容 (NC) 效应的分析预测模型。特别是，我们研究了铁电体厚度对 IV 特性的影响。重要的是，我们的模型预测负电容可最大限度地减少短沟道效应并增强电流过驱动，从而实现低功耗操作和更有效的晶体管尺寸缩放，而降低亚阈值斜率的影响显示系统性改进，在高电流水平下具有亚热离子亚阈值斜率值. 我们在长沟道无结 NC 中的预测结果显示，与无结 FET 相比，导通电流提高了 6 倍。这组方程可用作探索此类技术助推器及其缩放将如何影响器件在功率性能方面的主要品质因数的基础，并清楚地了解器件物理特性。分析模型的有效性通过与所有操作区域的数值 TCAD 模拟的广泛比较得到证实，从深度消耗到积累，从线性到饱和。