This article presents a power-efficient buffer-embedding successive approximation register (SAR) analog-to-digital converter (ADC) that utilizes a core power supply for the source-follower buffer, having a rail-to-rail signal swing due to the capacitive-level shifting bias scheme. Also, to implement the switched-capacitor (SC) level-shifting bias scheme without bias leakage issue, a negative boosting circuit is proposed. The boosting circuit is designed without any reliability issue, even with the use of thin-oxide transistors. For low-power applications, such as the biomedical system and CMOS image sensor, the proposed ADC incorporates a skip-reset (SR) scheme, a low-power delta-readout method. In conjunction with 8 $\times $ oversampling and the power-saving SR technique that has inherent chopping capability, a prototype SAR ADC fabricated in a 180-nm CMOS technology achieves a peak 74.8-dB signal-to-noise and distortion ratio (SNDR) and an 89.1-dB spurious free dynamic range (SFDR) for a 640-kHz bandwidth (BW) with an oversampling ratio (OSR) of 8, resulting in a Schreier figure of merit (FoM) of 167.3 dB. The chip area occupies 0.192 mm², and the power consumption is 180.1 $\mu \text{W}$ .

中文翻译：

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基于单电源 CDAC 的缓冲器嵌入 SAR ADC，具有固有斩波能力的跳过复位方案

本文介绍了一种高能效的缓冲器嵌入逐次逼近寄存器 (SAR) 模数转换器 (ADC)，它为源极跟随器缓冲器使用内核电源，由于电容电平转换偏置方案。此外，为了在没有偏置泄漏问题的情况下实现开关电容器 (SC) 电平移动偏置方案，提出了一种负升压电路。升压电路的设计没有任何可靠性问题，即使使用薄氧化物晶体管也是如此。对于低功耗应用，例如生物医学系统和 CMOS 图像传感器，建议的 ADC 结合了跳跃复位 (SR) 方案，这是一种低功耗增量读出方法。结合 8 $\times $ 过采样和具有固有斩波能力的节能 SR 技术，采用 180-nm CMOS 技术制造的原型 SAR ADC 实现了 74.8-dB 的峰值信噪比和失真比 (SNDR) 和 89.1-dB 的无杂散640 kHz 带宽 (BW) 的动态范围 (SFDR)，过采样率 (OSR) 为 8，导致 Schreier 品质因数 (FoM) 为 167.3 dB。芯片面积0.192 mm ²，功耗180.1 $\mu \text{W}$ .