This article presents a novel method for frequency tracking based on an extended bang-bang phase detector (XBBPD) in a referenceless clock and data recovery (CDR) circuit. The XBBPD-based structure has a frequency tracking range that completely covers the tuning range of the digitally controlled oscillator (DCO) with a fast locking feature. To minimize the loop delay and thereby improve the jitter tolerance, the CDR design includes an additional proportional path that is realized by directly controlling the phase of the oscillator with the output signal of the phase detector. The design is all-digital, including digital filters that simplify the design. The CDR occupies an active area of 0.031 mm2, implemented in a 28-nm CMOS process. The receiver operates up to 12.5 Gb/s. The frequency locking time, measured as the time required for every 1-Gb/s change in the input data, is 320 ns. The power consumption is only 21.13 mW, corresponding to an energy efficiency of 2.11 pJ/bit.

中文翻译：

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采用 28-nm CMOS 的 6.5-12.5-Gb/s 半速率单环全数字无参考 CDR

本文提出了一种基于无参考时钟和数据恢复 (CDR) 电路中的扩展 bang-bang 相位检测器 (XBBPD) 的频率跟踪新方法。基于 XBBPD 的结构具有频率跟踪范围，完全覆盖了具有快速锁定功能的数字控制振荡器 (DCO) 的调谐范围。为了最大限度地减少环路延迟，从而提高抖动容限，CDR 设计包括一个额外的比例路径，该路径通过使用鉴相器的输出信号直接控制振荡器的相位来实现。该设计是全数字的，包括简化设计的数字滤波器。CDR 占据 0.031 mm2 的有源面积，采用 28-nm CMOS 工艺实现。接收器的运行速度高达 12.5 Gb/s。锁频时间，输入数据每变化 1 Gb/s 所需的时间为 320 ns。功耗仅为 21.13 mW，对应的能效为 2.11 pJ/bit。