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Scalable benchmark synthesis for performance evaluation of NoC core mapping
Microprocessors and Microsystems ( IF 2.6 ) Pub Date : 2020-09-25 , DOI: 10.1016/j.micpro.2020.103272
Aruru Sai Kumar , T.V.K. Hanumantha Rao

Network On Chip is determined as an On-chip packet-switched communication in the study of multi-processors. As the number of components is proliferating, there were many issues regarding the performance of a network. By taking into consideration of this problem, in this paper, we proposed an efficient core mapping algorithm named BMAP, used for customizing the NoC platforms and performing the SPLASH-2 Benchmark synthesis evaluation. This proposed mapping technique is applied to various NoC applications and SPLASH-2 Benchmark applications. The experimental outcomes exhibit optimized NoC platforms on outperforming the performance and cost metrics when compared with other mapping algorithms. In contrast, the SPLASH-2 Benchmarks reveal that the proposed algorithm has a significant improvement in performance metrics against NMAP, MMAP, and EMAP algorithms. The metrics such as Speed-up Execution Time has improved by 40%, 30%, and 20%, and Latency reduced by 42%, 34%, and 28%, Energy efficiency was improved by 36%, 30%, 26%, and Power consumption reduced by 32.6%, 28.2%, and 26.4% respectively.



中文翻译:

可扩展的基准综合,用于NoC核心映射的性能评估

在多处理器研究中,片上网络被确定为片上分组交换通信。随着组件数量的激增,有关网络性能的问题很多。考虑到这一问题,本文提出了一种有效的核心映射算法,称为BMAP,用于自定义NoC平台并执行SPLASH-2 Benchmark综合评估。提议的映射技术已应用于各种NoC应用程序和SPLASH-2 Benchmark应用程序。与其他映射算法相比,实验结果展示出优化的NoC平台在性能和成本指标方面的出色表现。相比之下,SPLASH-2基准测试表明,该算法在针对NMAP,MMAP,和EMAP算法。加速执行时间等指标分别提高了40%,30%和20%,而延迟减少了42%,34%和28%,能源效率提高了36%,30%,26%,功耗分别降低了32.6%,28.2%和26.4%。

更新日期:2020-10-05
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