Ising chip based on uncertain behaviors of integrated circuits has been introduced to accelerate solving combinatorial optimization problem. However, the way to induce memory error by reducing supply voltage may also cause memory cells that represent interaction coefficients error, which will damage the original problem and obtain incorrect solution. This paper proposes a novel probability flipping method to realize Ising annealing chip by using circuit unreliability. It stores spins in 8-T SRAM and adjusts cell ratio to make it susceptible to circuit noise. Memory error is intentionally induced by reading the cell with high pre-charge bitline voltage and read upset rate can be controlled by the value of pre-charge voltage. The novel approach only probabilistically flips spins in the annealing process but have no influence on the interaction coefficients. Results show that circuit unreliability can be used to escape from local optimum for Ising annealing chip and improve computational performance.

引入了基于集成电路不确定行为的Ising芯片，以加速解决组合优化问题。然而，通过降低电源电压来引起存储器错误的方式也可能导致代表相互作用系数错误的存储器单元，这将损坏原始问题并获得错误的解决方案。提出了一种利用电路不可靠性实现伊辛退火芯片的概率倒装新方法。它将自旋存储在8-T SRAM中，并调整单元比以使其易于受到电路噪声的影响。通过读取具有高预充电位线电压的单元，有意引起存储错误，并且可以通过预充电电压的值来控制读取翻转速率。该新颖方法仅在退火过程中概率地使自旋翻转，但对相互作用系数没有影响。结果表明，电路的不可靠性可用于摆脱Ising退火芯片的局部最优值并提高计算性能。