Abstract

With the reduction of the technological dimensions of transistors, the influence of the variations of circuit and technological parameters on the values of the delay of the elements of combinational CMOS-circuits has grown significantly. Due to the spread of the values of these parameters, the uncertainty of delays appears, which leads to the necessity to define the ranges of possible delay values. The peak current in power lines when switching the inputs of gates is another factor increasingly influencing the design process of CMOS circuits in the transition to nanometer technologies. The value of the peak current is used to estimate the voltage drop in the power lines, which in turn is necessary to calculate the width of the power lines of CMOS circuits and switch off the transistors in the method of reducing the static power. The methods of full circuit simulation do not comprehensively analyze the circuits with a large number of inputs and the methods at the logical level of designing CMOS circuits do not provide the desired accuracy of the evaluation of the values of the delays and the peak current in the circuit. The problem of increasing the accuracy and the reliability of the analysis of the performance and peak currents of CMOS combinational circuits, taking into account the simultaneous switching of the inputs, as well as the analysis of logical correlations of the signals, is considered. The proposed method is based on using the cubic approximation of the correction difference of delays, taking into account the simultaneous switching of inputs. It is shown that the developed techniques of the analysis of the performance and peak currents of CMOS combinational circuits improve the accuracy of the upper estimates of the analyzed parameters by up to 3% compared with accurate simulation and make it possible to reduce the pessimistic upper estimate by factors of 2 to 3 compared with the estimate of the worst case. The developed methods of improving the accuracy of simulating delays and peak currents of combinational CMOS-circuits can be used as an addition to the existing CADS tools for VLSI for noise-immunity analysis, the analysis of the peak currents, characterization of complex functional units, and improving the accuracy of classical static analysis. To improving the accuracy of the interval estimates of the minimum delays and maximum peak current, the simulation methods taking into account the simultaneous switching of the inputs of the logical element are developed. In relation to the circuit simulation, the error of these methods does not exceed 3%. Compared with the results obtained without taking the simultaneous switching into account, reducing the minimum delay by up to 50% and the pessimistic estimate of the peak current of combinational circuits is reduced on average by 50–55%.

中文翻译：

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在逻辑设计水平上提高组合CMOS电路的延迟和峰值电流仿真精度的方法

摘要

随着晶体管技术尺寸的减小，电路和技术参数的变化对组合CMOS电路的元件的延迟值的影响显着增加。由于这些参数值的分布，出现了延迟的不确定性，这导致必须定义可能的延迟值的范围。在切换到栅极输入时，电源线中的峰值电流是在过渡到纳米技术时越来越多地影响CMOS电路设计过程的另一个因素。峰值电流值用于估计电源线中的电压降，而这又是计算CMOS电路电源线的宽度并以减小静态功率的方法关闭晶体管所必需的。全电路仿真的方法不能全面分析具有大量输入的电路，并且在设计CMOS电路的逻辑层次上的方法不能提供所需的评估延迟值和峰值电流的准确度。电路。考虑到考虑到输入的同时切换以及信号的逻辑相关性的分析，提高了CMOS组合电路的性能和峰值电流的分析的准确性和可靠性的问题。所提出的方法基于使用延迟校正差的三次近似，并考虑了输入的同时切换。结果表明，与精确仿真相比，所开发的CMOS组合电路的性能和峰值电流分析技术将分析参数的上限估计值的准确性提高了3％，并且有可能减少悲观的上限估计值与最坏情况的估计值相比，误差是2到3倍。为提高组合CMOS电路的延迟和峰值电流的仿真精度而开发的方法，可以用作现有用于VLSI的CADS工具的补充，用于噪声免疫分析，峰值电流分析，复杂功能单元的表征，并提高了经典静态分析的准确性。为了提高最小延迟和最大峰值电流的间隔估计的准确性，开发了考虑同时切换逻辑元件输入的仿真方法。关于电路仿真，这些方法的误差不超过3％。与不考虑同时切换的结果相比，将最小延迟降低了50％，并且对组合电路的峰值电流的悲观估计平均降低了50-55％。