We propose an architecture for a Field Programmable Gate Array (FPGA) based tester for a 3D stacked integrated circuit (IC). Due to the very short distances between dies in a stack that can make SerDes connections very efficient and the high density of through silicon vias (TSVs) that may be available, it is possible to connect the FPGA to the die under test through a very high bandwidth connection that can feed multiple short scan chains. We propose and evaluate two designs that exploit the underlying structure of the FPGA, allowing it to be used to efficiently store and apply predefined test patterns, reducing the FPGA resources required and the switching activity in the circuit under test when compared to a more traditional on-chip decompressor implemented to feed short scan chains. For the largest circuit we studied, the switching activity was reduced about 80% and the test time by 90%.

中文翻译：

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将 FPGA 重新用于测试仪设计以增强 3D 堆栈中的现场测试

我们为基于现场可编程门阵列 (FPGA) 的 3D 堆叠集成电路 (IC) 测试器提出了一种架构。由于堆栈中芯片之间的距离非常短，这可以使 SerDes 连接非常高效，并且可能提供高密度的硅通孔 (TSV)，因此可以通过非常高的速度将 FPGA 连接到被测芯片。可以提供多个短扫描链的带宽连接。我们提出并评估了两种利用 FPGA 底层结构的设计，使其能够有效地存储和应用预定义的测试模式，与更传统的测试模式相比，减少了所需的 FPGA 资源和被测电路中的开关活动。 -芯片解压器用于提供短扫描链。对于我们研究的最大电路，