Selecting the ideal trade-off between reliability improvement and cost (i.e., area, timing and power overhead) associated with a fault tolerant architecture generally requires an extensive Design Space Exploration. In this paper, we present a feasibility study that addresses the problem of selective hardening of arithmetic circuits by considering a duplication/comparison scheme as error detection architecture. Four different selective hardening methods have been investigated and compared: i) a full duplication scheme, ii) a reduced duplication scheme based on a structural susceptibility analysis, iii) a reduced duplication scheme based on the logical weight of the arithmetic circuit outputs and iv) a reduced duplication scheme that uses an approximate version of the arithmetic circuit. Experimental results performed on adder and multiplier case studies demonstrate the interest of using approximate structures in a duplication scheme since they provide much better error detection capability than other selective hardening methods with lower area and power overheads. Note that all experiments have been done without considering the area and power overhead due to the comparators. This may slightly biased the results from a quantitative point of view, although it does not jeopardize the main conclusion about the interest of using approximate structures as duplication scheme. Moreover, validations using a gate-level fault injection campaign have shown that approximate structures offer a better reliability level compared to the other considered duplication scenarios.

中文翻译：

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用近似计算建立算术电路的错误检测方案

在与容错架构相关的可靠性改进和成本（即面积、时序和功率开销）之间选择理想的权衡通常需要广泛的设计空间探索。在本文中，我们提出了一项可行性研究，该研究通过将复制/比较方案视为错误检测架构来解决算术电路的选择性硬化问题。已经研究和比较了四种不同的选择性硬化方法：i) 完全复制方案，ii) 基于结构敏感性分析的减少重复方案，iii) 基于算术电路输出的逻辑权重的减少重复方案和 iv)使用近似版本的算术电路的减少重复方案。在加法器和乘法器案例研究中执行的实验结果证明了在复制方案中使用近似结构的兴趣，因为它们比其他具有较低面积和功率开销的选择性硬化方法提供更好的错误检测能力。请注意，所有实验均未考虑由于比较器造成的面积和功率开销。从定量的角度来看，这可能会略微偏向结果，尽管它不会危及关于使用近似结构作为复制方案的兴趣的主要结论。此外，使用门级故障注入活动的验证表明，与其他考虑的重复场景相比，近似结构提供了更好的可靠性水平。