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Reliability of Fine-Pitch <5-μm-Diameter Microvias for High-Density Interconnects
IEEE Transactions on Components, Packaging and Manufacturing Technology ( IF 2.2 ) Pub Date : 2020-07-30 , DOI: 10.1109/tcpmt.2020.3013197 Shreya Dwarakanath , Takenori Kakutani , Daichi Okamoto , Pulugurtha Markondeya Raj , Madhavan Swaminathan , Rao R. Tummala
IEEE Transactions on Components, Packaging and Manufacturing Technology ( IF 2.2 ) Pub Date : 2020-07-30 , DOI: 10.1109/tcpmt.2020.3013197 Shreya Dwarakanath , Takenori Kakutani , Daichi Okamoto , Pulugurtha Markondeya Raj , Madhavan Swaminathan , Rao R. Tummala
Downscaling of package wiring has been the singular focus to achieve higher logic-memory interconnect density to meet next-generation needs for high-bandwidth computing. This article presents, for the first time, a systematic modeling and experimental study of sub-5-
$\mu \text{m}$
-diameter microvia reliability. Geometry design considerations and build-up dielectric material properties in evaluating the microvia fatigue life are investigated. Finally, experimental thermal-cycling reliability results of sub-5-
$\mu \text{m}$
-diameter microvias are correlated with the modeling results.
中文翻译:
细间距<5的可靠性μ 用于高密度互连的m直径微孔
缩小封装布线尺寸一直是实现更高逻辑存储互连密度以满足下一代对高带宽计算需求的唯一重点。本文首次介绍了Sub-5-的系统建模和实验研究 $ \ mu \ text {m} $
直径微孔可靠性。研究了评估微通孔疲劳寿命时的几何设计注意事项和堆积的电介质材料特性。最后,实验了5次子的热循环可靠性结果
$ \ mu \ text {m} $
直径的微孔与建模结果相关。
更新日期:2020-09-22
中文翻译:
细间距<5的可靠性
缩小封装布线尺寸一直是实现更高逻辑存储互连密度以满足下一代对高带宽计算需求的唯一重点。本文首次介绍了Sub-5-的系统建模和实验研究