This work presents an efficient ASIC implementation of successive cancellation (SC) decoder for polar codes. SC is a low-complexity depth-first search decoding algorithm, favorable for beyond-5G applications that require extremely high throughput and low power. The ASIC implementation of SC in this work exploits many techniques including pipelining and unrolling to achieve Tb/s data throughput without compromising power and area metrics. To reduce the complexity of the implementation, an adaptive log-likelihood ratio (LLR) quantization scheme is used. This scheme optimizes bit precision of the internal LLRs within the range of 1-5 bits by considering irregular polarization and entropy of LLR distribution in SC decoder. The performance cost of this scheme is less than 0.2 dB when the code block length is 1024 bits and the payload is 854 bits. Furthermore, some computations in SC take large space with high degree of parallelization while others take longer time steps. To optimize these computations and reduce both memory and latency, register reduction/balancing (R-RB) method is used. The final decoder architecture is called optimized polar SC (OPSC). The post-placement-routing results at 16nm FinFet ASIC technology show that OPSC decoder achieves 1.2 Tb/s coded throughput on 0.79 mm$^2$ area with 0.95 pJ/bit energy efficiency.

中文翻译：

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Tb/s 极性逐次消除解码器 16nm ASIC 实现

这项工作提出了极性码的连续消除 (SC) 解码器的有效 ASIC 实现。SC是一种低复杂度的深度优先搜索解码算法，适用于需要极高吞吐量和低功耗的超5G应用。在这项工作中，SC 的 ASIC 实现利用了许多技术，包括流水线和展开，以在不影响功率和面积指标的情况下实现 Tb/s 数据吞吐量。为了降低实现的复杂性，使用了自适应对数似然比 (LLR) 量化方案。该方案通过考虑SC解码器中LLR分布的不规则极化和熵，在1-5位范围内优化内部LLR的位精度。该方案在码块长度为1024位、载荷为854位时的性能成本小于0.2dB。此外，SC 中的一些计算占用大空间且并行化程度高，而其他计算则需要更长的时间步长。为了优化这些计算并减少内存和延迟，使用了寄存器减少/平衡 (R-RB) 方法。最终的解码器架构称为优化极性 SC (OPSC)。16nm FinFet ASIC 技术的布局后布线结果表明，OPSC 解码器在 0.79 mm$^2$ 面积上实现了 1.2 Tb/s 的编码吞吐量，并具有 0.95 pJ/bit 的能效。