Computationally expensive temperature and power grid analyses are required during the design cycle to guide IC design. This paper employs encoder-decoder based generative (EDGe) networks to map these analyses to fast and accurate image-to-image and sequence-to-sequence translation tasks. The network takes a power map as input and outputs the corresponding temperature or IR drop map. We propose two networks: (i) ThermEDGe: a static and dynamic full-chip temperature estimator and (ii) IREDGe: a full-chip static IR drop predictor based on input power, power grid distribution, and power pad distribution patterns. The models are design-independent and must be trained just once for a particular technology and packaging solution. ThermEDGe and IREDGe are demonstrated to rapidly predict the on-chip temperature and IR drop contours in milliseconds (in contrast with commercial tools that require several hours or more) and provide an average error of 0.6% and 0.008% respectively.

中文翻译：

---

使用卷积编码器-解码器网络进行热压降和 IR 压降分析

在设计周期中需要进行计算成本高昂的温度和电网分析来指导 IC 设计。本文采用基于编码器-解码器的生成 (EDGe) 网络将这些分析映射到快速准确的图像到图像和序列到序列的转换任务。网络以功率图作为输入并输出相应的温度或 IR 压降图。我们提出了两个网络：(i) ThermEDGe：静态和动态全芯片温度估计器和 (ii) IREDGe：基于输入功率、电网分布和电源焊盘分布模式的全芯片静态 IR 压降预测器。这些模型独立于设计，必须针对特定技术和包装解决方案进行一次培训。