Machine Learning (ML) has been applied in so many areas in reason of its robustness, usability, and reliability, mainly in hardware implementation. One of its well-known algorithms is the Support Vector Machine (SVM), the simplest to be applied in hardware because of its mathematical modeling. In this study, we propose the implementation in hardware of SVM multi-class classifiers within the asynchronous paradigm (i.e., without clock signal application) in a 4-stage pipeline architecture. With the purpose to evaluate the proposed architecture behavior, we used a Field Programmable Gate Array (FPGA) device to prototype the circuit. The proposed asynchronous SVM classifier is applied in a Speech Recognition system of 30 classes where a hybrid training algorithm was processed in the Matlab software, known as PSO-SVM training algorithm. Therefore, the training phase was processed in software in reason of its computational load. For the SVM classification phase, we propose, for the first time to the best of our knowledge, an asynchronous pipeline architecture of four stages with Multiply-Accumulator (MAC) unit application and three different control circuits described from Extended Burst-Mode (XBM) and State Transition Graph (STG) specifications, leading to energy-efficient design. In order to validate the SVM recognition results in the speech recognition application, the tests are from 60 speeches and 20 speakers, so it is a diversified and reliable data set of tests. The main goal here was to design a machine learning hardware implementation in a low power application and, through that, to prove that the asynchronous paradigm reduced power. As a result, we obtained a reduced power consumption of 5.72 mW, a fast average response time which was 0.61μs and the most area-efficient circuit (1315 LUTs); the accuracy in recognition success rate was another preoccupation, and it was very successful, 98% of success. Besides, we present comparisons with an asynchronous version of the same SVM datapath and with different synchronous architectures from literature to prove that our novelty is better in power consumption and area size. For hardware applications where low power and high performance are the sought features, the presented architecture revealed the best position when compared to similar works from the recent technical literature for pattern recognition systems.

机器学习（ML）由于其健壮性，可用性和可靠性而被广泛应用于许多领域，主要是在硬件实现方面。它的著名算法之一是支持向量机（SVM），由于其数学建模，它在硬件中最简单地应用。在这项研究中，我们提出了在4级流水线架构中的异步范例（即，没有时钟信号应用）中SVM多类分类器的硬件实现。为了评估所提出的体系结构行为，我们使用了现场可编程门阵列（FPGA）器件对该电路进行了原型设计。所提出的异步SVM分类器应用于30类语音识别系统，该系统在Matlab软件中处理了混合训练算法，即PSO-SVM训练算法。因此，由于其计算量大，因此在软件中处理了培训阶段。对于SVM分类阶段，我们首次据我们所知提出了一个异步管道体系结构，该体系结构包含四个阶段的乘法累加器（MAC）单元应用程序和扩展突发模式（XBM）中描述的三个不同控制电路和状态转换图（STG）规范，从而实现了节能设计。为了验证语音识别应用中的SVM识别结果，该测试来自60个语音和20个说话者，因此它是一组多样化且可靠的测试数据集。这里的主要目标是设计一种在低功耗应用程序中的机器学习硬件实现，并以此证明异步范例降低了功耗。结果是，我们降低了5.72 mW的功耗，快速的平均响应时间为0.61μs，电路效率最高（1315个LUT）。识别成功率的准确性是另一个问题，它非常成功，成功率为98％。此外，我们将比较与相同SVM数据路径的异步版本和文献中不同的同步体系结构进行比较，以证明我们的新颖性在功耗和面积方面更好。对于以低功耗和高性能为特征的硬件应用，与最近的模式识别系统技术文献中的类似作品相比，本架构显示了最佳位置。识别成功率的准确性是另一个问题，它非常成功，成功率为98％。此外，我们将比较与相同SVM数据路径的异步版本和文献中不同的同步体系结构进行比较，以证明我们的新颖性在功耗和面积方面更好。对于以低功耗和高性能为特征的硬件应用，与最近的模式识别系统技术文献中的类似作品相比，本架构显示了最佳位置。识别成功率的准确性是另一个问题，它非常成功，成功率为98％。此外，我们将比较与相同SVM数据路径的异步版本和文献中不同的同步体系结构进行比较，以证明我们的新颖性在功耗和面积方面更好。对于以低功耗和高性能为特征的硬件应用而言，与最新的模式识别系统技术文献中的类似作品相比，所展示的架构展现了最佳的位置。我们将同一个SVM数据路径的异步版本和文献中不同的同步体系结构进行比较，以证明我们的新颖性在功耗和面积方面更好。对于以低功耗和高性能为特征的硬件应用而言，与最新的模式识别系统技术文献中的类似作品相比，所展示的架构展现了最佳的位置。我们将同一个SVM数据路径的异步版本和文献中不同的同步体系结构进行比较，以证明我们的新颖性在功耗和面积方面更好。对于以低功耗和高性能为特征的硬件应用而言，与最新的模式识别系统技术文献中的类似作品相比，所展示的架构展现了最佳的位置。