Network-on-chips (NoCs) have emerged as communication backbones for enabling massive parallelism and high degree of integration in many-core chips. In spite of the advantages of conventional NoCs, wired multi-hop links impose limitations on NoCs performance by long delay and high power consumption especially in large systems. To alleviate these problems, different solutions such as wireless network-on-chip (WiNoC) designs have been proposed. WiNoCs benefit from long-range, high bandwidth and low power wireless links to solve problems corresponding to wired communications. Most of the WiNoC architectures have been designed based on mesh topology, while, honeycomb topology provides more energy-efficient NoC architecture with higher throughput than mesh topology, but, as we will show, a honeycomb-based WiNoC, by itself, does not reduce the amount of utilized hardware resources and delay. In this paper, we propose a hardware-efficient WiNoC with honeycomb topology, namely, H²WNoC aiming at reducing hardware resources, network cost, delay, and also energy consumption. Considering different performance parameters, cycle-accurate-based evaluations are performed for the proposed architecture; H²WNoC is compared with the traditional mesh WiNoC, as the baseline, and also with three state-of-the-art WiNoC architectures. Furthermore, design space exploration of the proposed architecture is performed. Performance evaluations indicate that H²WNoC utilizes less hardware resources, consumes less amount of energy and improves both throughput and delay, compared to the other WiNoC architectures. Moreover, the obtained results show that the proposed architecture outperforms wired NoCs either with mesh or honeycomb topology.

片上网络（NoC）已成为通信骨干，可在许多核心芯片中实现大规模并行性和高度集成。尽管具有常规NoC的优点，但有线多跳链路的延迟长和功耗高，特别是在大型系统中，对NoC的性能施加了限制。为了减轻这些问题，已经提出了诸如无线片上无线网络（WiNoC）设计之类的不同解决方案。WiNoC受益于远程，高带宽和低功率的无线链路，以解决与有线通信相对应的问题。大多数WiNoC架构都是基于网状拓扑设计的，而蜂窝状拓扑提供了比网状拓扑更节能的NoC架构，并具有更高的吞吐量，但是，正如我们将展示的，基于蜂窝的WiNoC本身，不会减少硬件资源的使用量和延迟。在本文中，我们提出了一种具有蜂窝拓扑的硬件高效的WiNoC，即H² WNoC旨在减少硬件资源，网络成本，延迟以及能耗。考虑到不同的性能参数，对所提出的体系结构进行了基于周期精确度的评估。将H ² WNoC与传统的网状WiNoC作为基准进行比较，并与三种最新的WiNoC体系结构进行比较。此外，对所提议的体系结构进行设计空间探索。性能评估表明，与其他WiNoC架构相比，H ² WNoC使用更少的硬件资源，消耗更少的能量，并提高了吞吐量和延迟。此外，获得的结果表明，无论是网状结构还是蜂窝拓扑结构，所提出的体系结构均优于有线NoC。