To decrease the parameters like: power dissipation, propagation delay and chip area in very-large-scale integration (VLSI) circuits, the gate-diffusion input (GDI) technique is convenient to be used. One of the most important functional blocks in frequency synthesizers is the dual-modulus frequency prescaler (DMFP) circuit. In this research work, we present novel powerful and robust designs which are part of proposed divide-by-N/[N+1] DMFP schemes for moduli set {N=1,2,3,4} with more efficiency, power storing and minimizing the gate counts using carbon nano-tube field-effect transistor (CNTFET)-based modified GDI (m-GDI) method. The simulation results of architectures in two standard CMOS and CNTFET technologies, clarified that the CNTFET-based proposed circuits are more effective in terms of critical path delay, power dissipation and worst delay-power consumption-chip area product (DPA) parameters. Also, according to the simulation results, presented DMFPs are capable to work at extensive evaluate frequency ranges with higher figure of merits (FOMs) at the maximum operating frequency (${\mathit{f}}_{max}$.). For the proposed circuit’s performance different variations process including diameter of CNTs, voltage and temperature (PVT) have been done by Monte-Carlo simulations. Thus, comparative analysis based on the Monte-Carlo simulation exhibits that the proposed structures show significant low-power consumption, sensitivity and larger noise-immunity in the presence of the impact of PVT variations. Therefore, the proposed DMFPs can be implemented in digital phase-locked loop (PLL) blocks for future wireless communication like: 5 Generation (5G) and microprocessor chips.

为了减少诸如超大规模集成电路（VLSI）电路中的功耗，传播延迟和芯片面积之类的参数，可以方便地使用栅极扩散输入（GDI）技术。频率合成器中最重要的功能模块之一是双模频率预分频器（DMFP）电路。在这项研究工作中，我们提出了新颖而强大的设计，它们是针对模数集{N = 1,2,3,4}的拟议的N / [N + 1] DMFP分频方案的一部分，具有更高的效率，功率存储并使用基于碳纳米管场效应晶体管（CNTFET）的改进GDI（m-GDI）方法最小化门数。两种标准CMOS和CNTFET技术的体系结构仿真结果表明，基于CNTFET的拟议电路在关键路径延迟方面更有效，DPA）参数。此外，根据仿真结果，提出的DMFP能够在广泛的评估频率范围内工作，并且在最大工作频率（FOM）时具有较高的品质因数（FOM）。${\mathit{F}}_{米\mathrm{一种}X}$）。对于所提出的电路的性能，已经通过蒙特卡洛仿真完成了包括CNT直径，电压和温度（PVT）在内的不同变化过程。因此，基于蒙特卡洛模拟的比较分析表明，在存在PVT变化影响的情况下，所提出的结构显示出显着的低功耗，灵敏度和较大的抗噪能力。因此，可以在数字锁相环（PLL）块中实现建议的DMFP，以用于未来的无线通信，例如：5代（5G）和微处理器芯片。