Strain is one of the conventional methods used to enhance the mobility of carriers in metal–oxide–semiconductor field-effect transistors (MOSFETs). The strain is generated due to the lattice mismatch between the thin Si layer and underlying SiGe layers and reduces the effective mass of holes and inter-subband scattering. A compact model for such devices is essential to promote the design of very large-scale integration (VLSI) circuits using strained p-MOSFETs. In this paper, for the first time we propose to use the BSIM3 model for biaxially strained p-MOSFETs, using a proper parameter extraction method. The extracted model parameters are validated by comparing the results with technology computer-aided design (TCAD) simulations and a simple analytical model. The average error in the direct-current (DC) and alternating-current (AC) characteristics of the model is estimated to be below 1.5%. Finally, the extracted model is used to analyze the performance of several digital gates, including inverter, NAND, NOR, and static random-access memory (SRAM) cells, based on the strained p-MOSFET as a key circuit component. The simulation results show significant performance improvements of the gates in terms of the area, propagation delay, dynamic power consumption, static noise margin, and functional symmetry. By using strained p-MOSFETs in the SRAM cell, the active area of transistors can be reduced by up to 28.8% while at the same the time static power consumption is reduced by 4.8%, the static noise margin is increased by 10.5%, and the write access time is reduced by about 15.6%. These results not only suggest that the strained Si p-MOSFET can improve the performance of VLSI circuits but also confirm that the BSIM3 model with an appropriate parameter extraction method can be used for the design of digital circuits using strained p-MOSFETs.

应变是用于增强金属氧化物半导体场效应晶体管（MOSFET）中载流子迁移率的常规方法之一。应变是由于薄Si层与下面的SiGe层之间的晶格失配而产生的，从而降低了空穴的有效质量和子带间散射。这种器件的紧凑模型对于促进使用应变p -MOSFET的超大规模集成电路（VLSI）的设计至关重要。在本文中，我们首次建议将BSIM3模型用于双轴应变p-MOSFET，使用适当的参数提取方法。通过将结果与技术计算机辅助设计（TCAD）仿真和简单的分析模型进行比较，可以验证所提取的模型参数。该模型的直流（DC）和交流（AC）特性的平均误差估计低于1.5％。最后，基于应变p- MOSFET作为关键电路组件，提取的模型用于分析几个数字门的性能，包括反相器，NAND，NOR和静态随机存取存储器（SRAM）单元。仿真结果表明，在面积，传播延迟，动态功耗，静态噪声容限和功能对称性方面，门的性能得到了显着改善。通过使用应变p-SRAM单元中的MOSFET，晶体管的有效面积可以减少多达28.8％，同时静态功耗减少了4.8％，静态噪声裕量增加了10.5％，并且写入访问时间减少了约15.6％。这些结果不仅表明应变Si p -MOSFET可以改善VLSI电路的性能，而且证实具有适当参数提取方法的BSIM3模型可以用于使用应变p -MOSFET的数字电路的设计。