The Rocket Chip Generator uses a collection of parameterized processor components to produce RISC-V-based SoCs. It is a powerful tool that can produce a wide variety of processor designs ranging from tiny embedded processors to complex multi-core systems. In this paper we extend the features of the Memory Management Unit of the Rocket Chip Generator and specifically the TLB hierarchy. TLBs are essential in terms of performance because they mitigate the overhead of frequent Page Table Walks, but may harm the critical path of the processor due to their size and/or associativity. In the original Rocket Chip implementation the L1 Instruction/Data TLB is fully-associative and the shared L2 TLB is direct-mapped. We lift these restrictions and design and implement configurable, set-associative L1 and L2 TLB templates that can create any organization from direct-mapped to fully-associative to achieve the desired ratio of performance and resource utilization, especially for larger TLBs. We evaluate different TLB configurations and present performance, area, and frequency results of our design using benchmarks from the SPEC2006 suite on the Xilinx ZCU102 FPGA.

中文翻译：

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使用火箭芯片生成器的可配置 TLB 层次结构在 RISC-V 上实现虚拟内存研究

Rocket Chip Generator 使用一组参数化处理器组件来生成基于 RISC-V 的 SoC。它是一个强大的工具，可以产生从微型嵌入式处理器到复杂的多核系统的各种处理器设计。在本文中，我们扩展了 Rocket Chip Generator 的内存管理单元的功能，特别是 TLB 层次结构。TLB 在性能方面是必不可少的，因为它们减轻了频繁的 Page Table Walks 的开销，但由于它们的大小和/或关联性，可能会损害处理器的关键路径。在最初的 Rocket Chip 实现中，L1 指令/数据 TLB 是完全关联的，而共享的 L2 TLB 是直接映射的。我们解除这些限制并设计和实现可配置的，设置关联的 L1 和 L2 TLB 模板，可以创建从直接映射到完全关联的任何组织，以实现所需的性能和资源利用率比率，尤其是对于较大的 TLB。我们使用来自赛灵思 ZCU102 FPGA 上的 SPEC2006 套件的基准来评估不同的 TLB 配置并展示我们设计的性能、面积和频率结果。