With technology scaling, subthreshold leakage has dominated the overall power consumption in a design. Input vector control is an effective technique to minimize subthreshold leakage. Low leakage input vector determination is not often possible due to large design space and simulation time. Similarly, applying an appropriate minimum leakage vector (MLV) to each Register Transfer Level (RTL) module instance in a design often results in a low leakage state with significant area overhead. In this work, we propose a top-down and bottom-up approach for propagating the input vector interval to identify low leakage input vector at primary inputs of an RTL datapath. For each module, via Monte Carlo simulation, we identify a set of MLV intervals such that maximum leakage is within (say) 10% of the lowest leakage points. As the module bit width increases, exhaustive simulation to find the low leakage vector is not feasible. Further, we need to uniformly search the entire input space to obtain as many low leakage intervals as possible. Based on empirical observations, we observe self-similarity in the subthreshold leakage distribution of adder/multiplier modules with highly regular bit-slice architectures when input space is partitioned into smaller cells. This property enables the uniform search of low leakage vectors in the entire input space where the time taken for characterization increases linearly with the module size. We further process the reduced interval set with simulated annealing to arrive at the best low-leakage vector at the primary inputs. We also propose to reduce area overhead (in some cases to 0%) by choosing Primary Input (PI) MLVs such that resultant inputs to internal nodes are also MLVs. Compared to existing work, experimental results for DSP filters simulated in 16nm technology demonstrated leakage savings of 93.6% and 89.2% for top-down and bottom-up approaches with no area overhead.

中文翻译：

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基于区间算术和自相似性的 RTL 输入矢量控制用于数据路径泄漏最小化

随着技术的扩展，亚阈值泄漏已经主导了设计中的整体功耗。输入矢量控制是一种减少亚阈值泄漏的有效技术。由于较大的设计空间和仿真时间，通常不可能确定低泄漏输入矢量。类似地，将适当的最小泄漏向量 (MLV) 应用于设计中的每个寄存器传输级别 (RTL) 模块实例通常会导致具有显着面积开销的低泄漏状态。在这项工作中，我们提出了一种自上而下和自下而上的方法来传播输入向量区间，以识别 RTL 数据路径的主要输入处的低泄漏输入向量。对于每个模块，通过蒙特卡罗模拟，我们确定了一组 MLV 间隔，使得最大泄漏在（例如）最低泄漏点的 10% 范围内。随着模块位宽的增加，穷举模拟来找到低泄漏向量是不可行的。此外，我们需要均匀地搜索整个输入空间，以获得尽可能多的低泄漏间隔。基于经验观察，当输入空间被划分为更小的单元时，我们观察到具有高度规则位片架构的加法器/乘法器模块的亚阈值泄漏分布的自相似性。此属性可以在整个输入空间中统一搜索低泄漏向量，其中表征所需的时间随模块大小线性增加。我们通过模拟退火进一步处理缩减的间隔集，以在主要输入处获得最佳的低泄漏向量。我们还建议通过选择主要输入 (PI) MLV 来减少区域开销（在某些情况下为 0%），这样内部节点的结果输入也是 MLV。与现有工作相比，在 16nm 技术中模拟的 DSP 滤波器的实验结果表明，自上而下和自下而上的方法可以节省 93.6% 和 89.2% 的泄漏，而没有面积开销。