Analogue-to-digital converters (ADC) using oversampling technology and the Σ-∆ modulation mechanism are widely applied in digital audio systems. This paper presents an audio modulator with high accuracy and low power consumption by using a discrete second-order feedforward structure. A 5-bit successive approximation register (SAR) quantizer is integrated into the chip, which reduces the number of comparators and the power consumption of the quantizer compared with flash ADC-type quantizers. An analogue passive adder is used to sum the input signals and it is embedded in a SAR ADC composed of a capacitor array and a dynamic comparator which has no static power consumption. To validate the design concept, the designed modulator is developed in a 180 nm CMOS process. The peak signal to noise distortion ratio (SNDR) is calculated as 106 dB and the total power consumption of the chip is recorded as 3.654 mW at the chip supply voltage of 1.8 V. The input sine wave of 0 to 25 kHz is sampled at a sampling frequency of 3.2 Ms/s. Moreover, the results achieve a 16-bit effective number of bits (ENOB) when the amplitude of the input signal is varied between 0.15 and 1.65 V. By comparing with other modulators which were realized by a 180 nm CMOS process, the proposed architecture outperforms with lower power consumption.

中文翻译：

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具有混合架构的低功耗Sigma-Delta调制器。

使用过采样技术和Σ-Δ调制机制的模数转换器（ADC）广泛应用于数字音频系统。本文提出了一种采用离散二阶前馈结构的高精度和低功耗音频调制器。该芯片中集成了一个5位逐次逼近寄存器（SAR）量化器，与闪存ADC类型的量化器相比，它减少了比较器的数量和量化器的功耗。模拟无源加法器用于对输入信号求和，并将其嵌入到由电容器阵列和动态比较器组成的SAR ADC中，该动态比较器没有静态功耗。为了验证设计概念，设计的调制器采用180 nm CMOS工艺开发。峰值信噪失真比（SNDR）计算为106 dB，芯片的总功耗在1.8 V的芯片电源电压下记录为3.654mW。0至25 kHz的输入正弦波在采样频率为3.2 Ms / s。此外，当输入信号的幅度在0.15V至1.65V之间变化时，结果可实现16位有效位数（ENOB）。与通过180 nm CMOS工艺实现的其他调制器进行比较，所提出的架构性能优于功耗更低。