Abstract The microwave interferometer is a device that works in the millimeter-wave frequency range, and it is used to measure the plasma density. The instability in the frequency source at the transmitter section of the interferometer affects the accuracy of the phase measurement in the receiver section. The phase-locked loop (PLL) circuit is a substantial unit in the generation of highly stable frequency. This paper proposes a highly stable frequency source generator for the D-band Microwave interferometer. The design, development, and analysis of the PLL system with the frequency signal of 6.9 GHz and 7.0 is presented in this paper. Two alternate approaches using the dielectric resonator oscillator (DRO) and Frequency synthesizer are presented to design the PLL circuit. The stability is achieved using a 7 GHz DRO in the transmitter section, which is phase-locked with a 6.9 GHz voltage controlled oscillator (VCO) at the receiver section in the proposed first design and a frequency synthesizer is used instead of DRO in the proposed second design. The developed circuit is analysed in terms of parameters like phase noise performance, output power level, development cost, design complexity, and operating frequency range. The PLL in the receiver section is configured using FPGA to analyze the circuit performance at various frequency offset. DRO generates the power of 17.62 dB m at a frequency of 7.0 GHz. The DRO and synthesizer circuit provides excellent phase noise performance of -120 dBc/Hz and -93 dBc/Hz, respectively, at the transmitter section and -94.12 dBc/Hz at the receiver section. Indigenous methods have been made for the development of PLLs. It will be used to develop a D-band microwave interferometer to measure the electron density of fusion plasma at the Institute for plasma research (IPR)-Government of India.

中文翻译：

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使用 PLL 在微波干涉仪中产生高度稳定的信号

摘要 微波干涉仪是一种工作在毫米波频率范围内的装置，用于测量等离子体密度。干涉仪发射器部分频率源的不稳定性会影响接收器部分相位测量的精度。锁相环 (PLL) 电路是产生高度稳定频率的重要单元。本文提出了一种用于 D 波段微波干涉仪的高度稳定的频率源发生器。本文介绍了频率信号为 6.9 GHz 和 7.0 的 PLL 系统的设计、开发和分析。介绍了使用介质谐振器振荡器 (DRO) 和频率合成器的两种替代方法来设计 PLL 电路。稳定性是在发射器部分使用 7 GHz DRO 实现的，在建议的第一种设计中，它在接收器部分使用 6.9 GHz 压控振荡器 (VCO) 进行锁相，并且在建议的第二种设计中使用频率合成器代替 DRO。根据相位噪声性能、输出功率电平、开发成本、设计复杂性和工作频率范围等参数对开发的电路进行分析。接收器部分的 PLL 使用 FPGA 进行配置，以分析各种频率偏移下的电路性能。DRO 在 7.0 GHz 的频率下产生 17.62 dB m 的功率。DRO 和合成器电路在发射器部分和接收器部分分别提供 -120 dBc/Hz 和 -93 dBc/Hz 的出色相位噪声性能。已经为开发 PLL 制定了本土方法。