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Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation.
Micromachines ( IF 3.4 ) Pub Date : 2020-09-13 , DOI: 10.3390/mi11090852
Jong Hyeok Oh 1 , Yun Seop Yu 1
Affiliation  

The optimal structure and process for the feedback field-effect transistor (FBFET) to operate as a logic device are investigated by using a technology computer-aided design mixed-mode simulator. To minimize the memory window of the FBFET, the channel length (Lch), thickness of silicon body (Tsi), and doping concentration (Nch) of the channel region below the gate are adjusted. As a result, the memory window increases as Lch and Tsi increase, and the memory window is minimum when Nch is approximately 9 × 1019 cm−3. The electrical coupling between the top and bottom tiers of a monolithic 3-dimensional inverter (M3DINV) consisting of an n-type FBFET located at the top tier and a p-type FBFET located at the bottom tier is also investigated. In the M3DINV, we investigate variation of switching voltage with respect to voltage transfer characteristics (VTC), with different thickness values of interlayer dielectrics (TILD), Tsi, Lch, and Nch. The variation of propagation delay of the M3DINV with different TILD, Tsi, Lch, and Nch is also investigated. As a result, the electrical coupling between the stacked FBFETs by TILD can be neglected. The switching voltage gaps increase as Lch and Tsi increase and decrease, respectively. Furthermore, the slopes of VTC of M3DINV increase as Tsi and Nch increase. For transient response, tpHL decrease as Lch, Tsi, and Nch increase, but tpLH increase as Lch and Tsi increase and it is almost the same for Nch.

中文翻译:

使用TCAD仿真研究带有反馈场效应晶体管的单片3D集成电路逆变器。

通过使用计算机辅助设计的混合模式仿真器技术,研究了反馈场效应晶体管(FBFET)用作逻辑器件的最佳结构和过程。为了最小化FBFET的存储窗口,调整了栅极下方的沟道区的沟道长度(L ch),硅体厚度(T si)和掺杂浓度(N ch)。结果,随着L chT si增大,存储窗口增大,并且当N ch约为9×10 19 cm -3时,存储窗口最小。。还研究了由位于顶层的n型FBFET和位于底层的p型FBFET组成的整体式3维逆变器(M3DINV)的顶层和底层之间的电耦合。在M3DINV中,我们研究了开关电压相对于电压传递特性(VTC)的变化,其中层间电介质的厚度值(T ILD),T siL chN ch的厚度不同。M3DINV的传播延迟随T ILDT siL chN ch的变化而变化也进行了调查。其结果,通过层叠FBFETs之间的电耦合Ť ILD可以忽略不计。开关电压间隙分别随着L chT si的增加和减少而增加。此外,M3DINV的VTC斜率随着T siN ch的增加而增加。对于瞬态响应,t pHL随着L chT siN ch的增加而降低,而t pLH随着L chT si的增加而增加N ch几乎相同。
更新日期:2020-09-13
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