FinFETs are predicted to advance semiconductorscaling for sub-20nm devices. In order to support their intro-duction into research and universities it is crucial to develop anopen source predictive process design kit. This paper discussesin detail the design process for such a kit for 15nm FinFETdevices, called the FreePDK15. The kit consists of a layerstack with thirteen-metal layers based on hierarchical-scalingused in ASIC architecture, Middle-of-Line local interconnectlayers and a set of Front-End-of-Line layers. The physical andgeometrical properties of these layers are defined and theseproperties determine the density and parasitics of the design. Thedesign rules are laid down considering additional guidelines forprocess variability, challenges involved in FinFET fabrication anda unique set of design rules are developed for critical dimensions.Layout extraction including modified rules for determining thegeometrical characteristics of FinFET layouts are implementedand discussed to obtain successful Layout Versus Schematicchecks for a set of layouts. Moreover, additional parasiticcomponents of a standard FinFET device are analyzed andthe parasitic extraction of sample layouts is performed. Theseextraction results are then compared and assessed against thevalidation models.

中文翻译：

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为 15 纳米 FinFET 开发预测性工艺设计套件：FreePDK15

预计 FinFET 将推动亚 20 纳米器件的半导体规模化。为了支持将它们引入研究和大学，开发开源预测过程设计工具包至关重要。本文详细讨论了此类用于 15 纳米 FinFET 器件的套件（称为 FreePDK15）的设计过程。该套件由基于 ASIC 架构中使用的分层缩放的 13 个金属层的层堆栈、线中局部互连层和一组线前端层组成。定义了这些层的物理和几何特性，这些特性决定了设计的密度和寄生效应。设计规则的制定考虑了过程可变性的附加指南，FinFET 制造中涉及的挑战，并针对关键尺寸开发了一组独特的设计规则。 实施并讨论了包括用于确定 FinFET 布局几何特征的修改规则在内的布局提取，以获得成功的布局与一组布局的原理图检查。此外，还分析了标准 FinFET 器件的附加寄生分量，并执行了样本布局的寄生提取。然后将这些提取结果与验证模型进行比较和评估。分析标准 FinFET 器件的附加寄生成分，并执行样本布局的寄生提取。然后将这些提取结果与验证模型进行比较和评估。分析标准 FinFET 器件的附加寄生成分，并执行样本布局的寄生提取。然后将这些提取结果与验证模型进行比较和评估。