In this article, we propose a fine-grained FPGA aging mitigation method. Our method focuses on Look Up Tables (LUTs) on which Boolean functions are mapped. Based on our observations, for any configuration, even if it is carefully selected, a number of LUT transistors experience severe stress rates. Therefore, an algorithm is presented to select several alternative configurations for each LUT. Alternative configurations are obtained by LUT input reordering. These alternative configurations are rotationally loaded into the FPGA. Experimental results shows that our method achieves 263 and 14.1 percent Mean Time To Failure (MTTF) improvement for Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI), respectively. Additionally, due to changing only local routings, our method imposes up to 1 percent performance overhead to the systems.

中文翻译：

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LUT 输入重新排序以减少对 FPGA LUT 的老化影响

在本文中，我们提出了一种细粒度的 FPGA 老化缓解方法。我们的方法侧重于映射布尔函数的查找表 (LUT)。根据我们的观察，对于任何配置，即使经过精心选择，许多 LUT 晶体管也会经历严重的应力率。因此，提出了一种算法来为每个 LUT 选择几个替代配置。通过 LUT 输入重新排序获得替代配置。这些替代配置被轮流加载到 FPGA 中。实验结果表明，我们的方法分别将热载流子注入 (HCI) 和偏置温度不稳定性 (BTI) 的平均无故障时间 (MTTF) 提高了 263% 和 14.1%。此外，由于仅更改本地路由，我们的方法会给系统带来高达 1% 的性能开销。