The metal–semiconductor (MES)-based through silicon vias (TSV) has provided attractive solutions over conventional metal–insulator–semiconductor (MIS) TSVs in recent three-dimensional (3D) integration. This paper aims a comprehensive performance analysis of MIS and MES structures considering different TSV shapes such as cylindrical, tapered, annular, and square. At 32nm technology, a CMOS-based coupled driver-via-load (DVL) setup is introduced wherein each via is represented an equivalent RLGC model of MIS- and MES-based TSV shapes. The proposed electrical model accurately considers the impact of micro bump and inter-metal dielectric (IMD) effects at 32nm technology as per the fabrication house. A 3D electromagnetic (EM) structural wave simulation is performed to validate the RLGC model parameters of different TSV structures for an operating frequency of up to 20GHz. The proposed DVL setup is used to analyze the propagation delay, power dissipation, and dynamic crosstalk for different MIS- and MES-based TSV shapes. A significant improvement in the cross-coupling behavior can be obtained using the MES-based tapered TSV compared to the other MIS structures. Additionally, the power delay product (PDP) of the tapered MES is reduced by 92.4% compared to the conventional MIS-based cylindrical TSV.

中文翻译：

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硅通孔在 3D 集成中的作用：对延迟和功率的影响

在最近的三维 (3D) 集成中，基于金属-半导体 (MES) 的硅通孔 (TSV) 提供了优于传统金属-绝缘体-半导体 (MIS) TSV 的有吸引力的解决方案。本文旨在对 MIS 和 MES 结构进行综合性能分析，考虑不同的 TSV 形状，如圆柱形、锥形、环形和方形。32 岁nm 技术，引入了基于 CMOS 的耦合驱动通孔负载 (DVL) 设置，其中每个通孔表示一个等效的RLGC基于 MIS 和 MES 的 TSV 形状模型。所提出的电气模型准确地考虑了微凸块和金属间介电 (IMD) 效应在 32根据制造厂的纳米技术。执行 3D 电磁 (EM) 结构波模拟以验证RLGC工作频率高达 20 的不同 TSV 结构的模型参数千兆赫。建议的 DVL 设置用于分析不同基于 MIS 和 MES 的 TSV 形状的传播延迟、功耗和动态串扰。与其他 MIS 结构相比，使用基于 MES 的锥形 TSV 可以获得交叉耦合行为的显着改进。此外，与传统的基于 MIS 的圆柱形 TSV 相比，锥形 MES 的功率延迟积 (PDP) 降低了 92.4%。