Developing an analog-to-digital converter (ADC) based on the time-interleaved delta–sigma modulator (TIDSM) is an appropriate technique to attain high-speed ADCs. TIDSMs can be successfully accomplished with the aid of developing the block digital filtering (BDF) method. In this approach, M mutually cross-connection delta–sigma modulators are used, whereby each one of them operates at a sampling rate of fs, leading to an effective sampling rate of M∗fs. In this study, a novel structure is proposed based on the Noise Coupled time-interleaved delta–sigma modulator (NC-TIDSM) with reduced hardware complexity. This structure not only increases the overall noise transfer function (NTF) order, but also reduces the hardware element counts. The simulation results demonstrate that the SNDRs of the first-order two-channel and four-channel NC-TIDSM with reduced hardware are 13 and 15 dB better than those of their BDF technique counterparts; also, the SNDR of the second-order two-channel NC-TIDSM with reduced hardware is 8 dB better than that of their BDF technique counterpart; also, the hardware element quantities are reduced dramatically. Moreover, some practical challenges such as the finite op-amp’s gain and mismatching effects that directly affect the circuit implementation of the proposed structure have been described. Furthermore, the hardware complexity of the proposed structures is reduced considerably in comparison to that of the BDF technique with the NC-TIDSM structure.

中文翻译：

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降低硬件复杂度的噪声耦合时间交错 Δ-Σ 调制器

开发基于时间交错 Δ-Σ 调制器 (TIDSM) 的模数转换器 (ADC) 是获得高速 ADC 的合适技术。借助开发块数字滤波 (BDF) 方法，可以成功实现 TIDSM。在这种方法中，米使用相互交叉连接的 delta-sigma 调制器，其中每个调制器以Fs，导致有效的采样率米*Fs. 在这项研究中，提出了一种基于噪声耦合时间交错 delta-sigma 调制器 (NC-TIDSM) 的新型结构，降低了硬件复杂性。这种结构不仅增加了整体噪声传递函数 (NTF) 阶数，而且还减少了硬件元件数量。仿真结果表明，减少硬件的一阶二通道和四通道 NC-TIDSM 的 SNDR 分别比其 BDF 技术对应物好 13 dB 和 15 dB；此外，减少硬件的二阶双通道 NC-TIDSM 的 SNDR 比其 BDF 技术对应物好 8 dB；此外，硬件元件数量也大大减少。而且，已经描述了一些实际挑战，例如直接影响所提出结构的电路实现的有限运算放大器的增益和失配效应。此外，与具有 NC-TIDSM 结构的 BDF 技术相比，所提出结构的硬件复杂性大大降低。