A trade-off switching scheme between high efficiency and considerable area overhead for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. During the design process, the higher-side-reset-and-set (HSRS) coarse–fine architecture ensures significant energy saving. There is no energy consumption in the first two comparison cycles. The presented switching scheme achieves 99.15% savings in switching energy and 92.1% reduction in total capacitance, compared with the conventional SAR ADC. Benefit from the HSRS method, an improved HSRS scheme is proposed to reduce the switching energy in the coarse quantization process, achieving 1/16CV²_ref energy saving for the third comparison cycle compared with HSRS method. Furthermore, the reset energy is verified to be 0.1367CV²_ref due to the energy-free charge distribution and capacitor multiplexing (CDCM) technology adopted in the fine quantization process.

提出了一种在连续逼近寄存器（SAR）模数转换器（ADC）的高效率和大量面积开销之间进行权衡的切换方案。在设计过程中，较高侧的复位和设定（HSRS）粗精细结构可确保大量节能。在前两个比较周期中没有能耗。与传统的SAR ADC相比，本发明的开关方案可节省99.15％的开关能量，并减少92.1％的总电容。受益于HSRS方法，提出了一种改进的HSRS方案，以减少粗量化过程中的开关能量，与HSRS方法相比，在第三个比较周期中实现了1 / 16CV ² _ref 节能。此外，复位能量经验证为0.1367CV² _ref是 由于精细量化过程中采用了无能量电荷分配和电容器多路复用（CDCM）技术。