As the process feature size continues to scale down, the susceptibility of logic circuits to radiation induced error has increased. This trend has led to the increase in sensitivity of circuits to multi-node upsets. Previously, work has been done to harden latches against single event upsets (SEU). Currently, there has been a concerted effort to design latches that are tolerant to double node upsets (DNU) and triple node upsets (TNU). In this paper, we first propose a novel DNU tolerant latch design. The latch is designed specifically to provide additional reliability when clock gating is used. Through experimentation, it is shown that the DNU tolerant latch is 11.3 percent more power efficient than existing latch designs suited for clock gating. In addition to the DNU tolerant design, we propose the first TNU tolerant latch. The TNU tolerant latch is shown to provide superior soft error resiliency while incurring a 40 percent overhead compared to DNU tolerant designs.

中文翻译：

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用于双节点和三节点翻转的抗辐射闩锁设计

随着工艺特征尺寸继续缩小，逻辑电路对辐射引起的误差的敏感性增加了。这种趋势导致电路对多节点干扰的敏感性增加。以前，已经完成了针对单事件翻转 (SEU) 强化锁存器的工作。目前，人们共同努力设计能够承受双节点翻转 (DNU) 和三节点翻转 (TNU) 的锁存器。在本文中，我们首先提出了一种新颖的 DNU 容错锁存器设计。锁存器专门设计用于在使用时钟门控时提供额外的可靠性。实验表明，与适用于时钟门控的现有锁存器设计相比，DNU 容错锁存器的能效提高了 11.3%。除了 DNU 容错设计之外，我们还提出了第一个 TNU 容错锁存器。