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Memory Physical Aware Multi-Level Fault Diagnosis Flow
IEEE Transactions on Emerging Topics in Computing ( IF 5.9 ) Pub Date : 2020-07-01 , DOI: 10.1109/tetc.2018.2789818
Gurgen Harutyunyan , Suren Martirosyan , Samvel Shoukourian , Yervant Zorian

Advanced methods of fault detection and diagnosis become increasingly important for the improvement of reliability, safety and efficiency in nanoscale designs. Because the existing approaches do not give a deeper insight and usually do not allow a comprehensive fault diagnosis, multi-level model based methods of fault detection were developed by using hierarchy of detection and diagnosis methods. This contribution proposes a memory physical (scrambling) aware multi-level fault diagnosis flow which is generic and applicable both for planar- and FinFET-based memories. In addition, special test algorithms for classification of static and dynamic faults are discussed while for classification of FinFET-specific faults a new test algorithm March FFDD is proposed. The flow is validated on 16nm FPGA board as well as it has been applied to numerous chips enabling successful physical failure analysis (PFA). At the end of the paper some real-life case scenarios of the flow application are presented.

中文翻译:

内存物理感知多级故障诊断流程

先进的故障检测和诊断方法对于提高纳米级设计的可靠性、安全性和效率变得越来越重要。由于现有方法不能提供更深入的洞察力,并且通常不允许进行全面的故障诊断,因此通过使用层次检测和诊断方法开发了基于多级模型的故障检测方法。该贡献提出了一种内存物理(加扰)感知多级故障诊断流程,该流程通用且适用于基于平面和 FinFET 的内存。此外,讨论了用于静态和动态故障分类的特殊测试算法,而对于 FinFET 特定故障的分类,提出了一种新的测试算法 March FFDD。该流程在 16 纳米 FPGA 板上得到验证,并且已应用于众多芯片,实现成功的物理故障分析 (PFA)。在论文的最后,介绍了流应用程序的一些真实案例场景。
更新日期:2020-07-01
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