While inclusion of emerging technology-based Non-Volatile Memory (NVM) devices in on-chip memory subsystems offers excellent potential for energy savings and scalability, their sensing vulnerability creates Process Variation (PV) challenges. This paper presents a circuit-architecture cross-layer solution to realize a radically-different approach to leveraging as-built variations via specific Sense Amplifier (SA) design and use. This novel approach, referred to as a Self-Organized Sub-bank (SOS) design, assigns the preferred SA to each Sub-Bank (SB) based on a PV assessment, resulting in energy consumption reduction and increased read access reliability. To improve the PV immunity of SAs, two reliable and power efficient SAs, called the Merged SA (MSA) and the Adaptive SA (ASA) are introduced herein for use in the SOS scheme. Furthermore, we propose a dynamic PV and energy-aware cache block migration policy that utilizes mixed SRAM and STT-MRAM banks in Last Level Cache (LLC) to maximize the SOS bandwidth. Our experimental results indicate that SOS can alleviate the sensing vulnerability by 89 percent on average, which significantly reduces the risk of application contamination by fault propagation. Furthermore, in the light of the proposed block migration policy, write performance is improved by 12.4 percent on average compared to the STT-MRAM-only design.

中文翻译：

---

减轻非易失性缓存弹性和产量的过程可变性

虽然在片上存储器子系统中包含基于新兴技术的非易失性存储器 (NVM) 设备为节能和可扩展性提供了极好的潜力，但它们的传感脆弱性带来了工艺变化 (PV) 挑战。本文提出了一种电路架构跨层解决方案，以实现一种完全不同的方法，通过特定的检测放大器 (SA) 设计和使用来利用竣工变化。这种称为自组织子库 (SOS) 设计的新颖方法根据 PV 评估将首选 SA 分配给每个子库 (SB)，从而降低能耗并提高读取访问可靠性。为了提高 SA 的 PV 抗扰性，本文引入了两种可靠且节能的 SA，称为合并 SA (MSA) 和自适应 SA (ASA)，用于 SOS 方案。此外，我们提出了一种动态 PV 和能量感知缓存块迁移策略，该策略利用最后一级缓存 (LLC) 中的混合 SRAM 和 STT-MRAM 组来最大化 SOS 带宽。我们的实验结果表明，SOS 可以将感知漏洞平均降低 89%，从而显着降低故障传播导致应用程序污染的风险。此外，根据提议的块迁移策略，与仅使用 STT-MRAM 的设计相比，写入性能平均提高了 12.4%。这显着降低了由故障传播引起的应用程序污染的风险。此外，根据提议的块迁移策略，与仅使用 STT-MRAM 的设计相比，写入性能平均提高了 12.4%。这显着降低了由故障传播引起的应用程序污染的风险。此外，根据提议的块迁移策略，与仅使用 STT-MRAM 的设计相比，写入性能平均提高了 12.4%。