The hot carrier (HC) induced degradation has become a major concern in advanced CMOS technologies because of non-scalable $\text{V}_{\mathrm{ DD}}$ . In this work, we have shown that the HC induced degradation in gate-first HKMG nMOS transistors can be modulated by optimizing the device width, lanthanum capping layer thickness, and pre-gate carbon (C) implant. The physics responsible for these observations are investigated and attributed to the reduction in the number of defects (traps) in hafnium oxide (HfO₂) and reduction in carrier injection into these defects. It is also shown that the HC performance of these transistors could be further improved by increasing the active-to-active spacing.

中文翻译：

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器件尺寸、布局和栅极前碳注入对 HKMG nMOS 晶体管中热载流子诱导退化的影响

由于不可扩展，热载流子 (HC) 引起的退化已成为先进 CMOS 技术的主要问题 $\text{V}_{\mathrm{ DD}}$ . 在这项工作中，我们已经表明，可以通过优化器件宽度、镧覆盖层厚度和栅极前碳 (C) 注入来调节栅极优先 HKMG nMOS 晶体管中 HC 引起的退化。研究了导致这些观察结果的物理学，并将其归因于氧化铪 (HfO ₂ )中缺陷（陷阱）数量的减少和载流子注入这些缺陷的减少。还表明，通过增加有源到有源的间距，可以进一步提高这些晶体管的 HC 性能。