Fine-grained runtime power management techniques could be promising solutions for power reduction. Therefore, it is essential to establish accurate power monitoring schemes to obtain dynamic power variation in a short period (i.e., tens or hundreds of clock cycles). In this paper, we leverage a decision-tree-based power modeling approach to establish fine-grained hardware power monitoring on FPGA platforms. A generic and complete design flow is developed to implement the decision tree power model which is capable of precisely estimating dynamic power in a fine-grained manner. A flexible architecture of the hardware power monitoring is proposed, which can be instrumented in any RTL design for runtime power estimation, dispensing with the need for extra power measurement devices. Experimental results of applying the proposed model to benchmarks with different resource types reveal an average error up to 4% for dynamic power estimation. Moreover, the overheads of area, power and performance incurred by the power monitoring circuitry are extremely low. Finally, we apply our power monitoring technique to the power management using phase shedding with an on-chip multi-phase regulator as a proof of concept and the results demonstrate 14% efficiency enhancement for the power supply of the FPGA internal logic.

中文翻译：

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基于决策树的硬件电源监控，用于 FPGA 中的运行时动态电源管理

细粒度的运行时电源管理技术可能是降低功耗的有前途的解决方案。因此，必须建立准确的功率监控方案，以获得短时间内（即数十或数百个时钟周期）的动态功率变化。在本文中，我们利用基于决策树的功耗建模方法在 FPGA 平台上建立细粒度的硬件功耗监控。开发了通用且完整的设计流程来实现决策树功耗模型，该模型能够以细粒度的方式精确估计动态功耗。提出了一种灵活的硬件功率监控架构，可以在任何 RTL 设计中进行检测以进行运行时功率估计，无需额外的功率测量设备。将所提出的模型应用于具有不同资源类型的基准的实验结果表明，动态功率估计的平均误差高达 4%。此外，功率监控电路所产生的面积、功率和性能开销极低。最后，我们将我们的电源监控技术应用到电源管理中，使用切相和片上多相稳压器作为概念验证，结果表明 FPGA 内部逻辑的电源效率提高了 14%。