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Building Application-Specific Overlays on FPGAs with High-Level Customizable IPs
arXiv - CS - Programming Languages Pub Date : 2020-09-01 , DOI: arxiv-2009.00637
Hongbo Rong

Overlays are virtual, re-configurable architectures that overlay on top of physical FPGA fabrics. An overlay that is specialized for an application, or a class of applications, offers both fast reconfiguration and minimized performance penalty. Such an overlay is usually implemented by hardware designers in hardware "assembly" languages at register-transfer level (RTL). This short article proposes an idea for a software programmer, instead of hardware designers, to quickly implement an application-specific overlay using high-level customizable IPs. These IPs are expressed succinctly by a specification language, whose abstraction level is much higher than RTL but can nonetheless expresses many performance-critical loop and data optimizations on FPGAs, and thus would offer competitively high performance at a much lower cost of maintenance and much easier customizations. We propose new language features to easily put the IPs together into an overlay. A compiler automatically implements the specified optimizations to generate an efficient overlay, exposes a multi-tasking programming interface for the overlay, and inserts a runtime scheduler for scheduling tasks to run on the IPs of the overlay, respecting the dependences between the tasks. While an application written in any language can take advantage of the overlay through the programming interface, we show a particular usage scenario, where the application itself is also succinctly specified in the same language. We describe the new language features for expressing overlays, and illustrate the features with an LU decomposer and a convolutional neural network. A system is under construction to implement the language features and workloads.

中文翻译:

使用高级可定制 IP 在 FPGA 上构建特定于应用的覆盖

覆盖层是虚拟的、可重新配置的架构,覆盖在物理 FPGA 架构之上。专用于一个应用程序或一类应用程序的覆盖提供快速重新配置和最小化性能损失。这种覆盖通常由硬件设计人员在寄存器传输级 (RTL) 的硬件“汇编”语言中实现。这篇简短的文章为软件程序员而不是硬件设计师提出了一个想法,即使用高级可定制 IP 快速实现特定于应用程序的覆盖。这些 IP 用一种规范语言简洁地表达,其抽象级别远高于 RTL,但仍然可以在 FPGA 上表达许多性能关键的循环和数据优化,从而以更低的维护成本和更容易的定制提供具有竞争力的高性能。我们提出了新的语言功能,可以轻松地将 IP 放在一个叠加层中。编译器自动实施指定的优化以生成高效的覆盖层,为覆盖层公开多任务编程接口,并插入运行时调度程序以调度任务以在覆盖层的 IP 上运行,尊重任务之间的依赖关系。虽然用任何语言编写的应用程序都可以通过编程接口利用覆盖,但我们展示了一个特定的使用场景,其中应用程序本身也用相同的语言简洁地指定。我们描述了用于表达叠加的新语言特性,并用 LU 分解器和卷积神经网络说明特征。正在构建一个系统来实现语言功能和工作负载。
更新日期:2020-09-03
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