High-level synthesis (HLS) enables designers to customize hardware designs efficiently. However, it is still challenging to foresee the correlation between power consumption and HLS-based applications at an early design stage. To overcome this problem, we introduce HL-Pow, a power modeling framework for FPGA HLS based on state-of-the-art machine learning techniques. HL-Pow incorporates an automated feature construction flow to efficiently identify and extract features that exert a major influence on power consumption, simply based upon HLS results, and a modeling flow that can build an accurate and generic power model applicable to a variety of designs with HLS. By using HL-Pow, the power evaluation process for FPGA designs can be significantly expedited because the power inference of HL-Pow is established on HLS instead of the time-consuming register-transfer level (RTL) implementation flow. Experimental results demonstrate that HL-Pow can achieve accurate power modeling that is only 4.67% (24.02 mW) away from onboard power measurement. To further facilitate power-oriented optimizations, we describe a novel design space exploration (DSE) algorithm built on top of HL-Pow to trade off between latency and power consumption. This algorithm can reach a close approximation of the real Pareto frontier while only requiring running HLS flow for 20% of design points in the entire design space.

中文翻译：

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HL-Pow：用于高级综合的基于学习的功率建模框架

高级综合 (HLS) 使设计人员能够有效地定制硬件设计。然而，在早期设计阶段预测功耗与基于 HLS 的应用之间的相关性仍然具有挑战性。为了克服这个问题，我们引入了 HL-Pow，这是一种基于最先进机器学习技术的 FPGA HLS 电源建模框架。HL-Pow 结合了一个自动化的特征构建流程，以有效地识别和提取对功耗产生重大影响的特征，只需基于 HLS 结果，以及一个建模流程，可以构建适用于各种设计的准确和通用的功耗模型HLS。通过使用 HL-Pow，FPGA 设计的功耗评估过程可以显着加快，因为 HL-Pow 的功耗推断是在 HLS 上建立的，而不是耗时的寄存器传输级 (RTL) 实现流程。实验结果表明，HL-Pow 可以实现精确的功率建模，与板载功率测量仅相差 4.67% (24.02 mW)。为了进一步促进面向功耗的优化，我们描述了一种建立在 HL-Pow 之上的新颖设计空间探索 (DSE) 算法，以在延迟和功耗之间进行权衡。该算法可以非常接近真实的帕累托边界，同时只需要对整个设计空间中 20% 的设计点运行 HLS 流。实验结果表明，HL-Pow 可以实现精确的功率建模，与板载功率测量仅相差 4.67% (24.02 mW)。为了进一步促进面向功耗的优化，我们描述了一种建立在 HL-Pow 之上的新颖设计空间探索 (DSE) 算法，以在延迟和功耗之间进行权衡。该算法可以非常接近真实的帕累托边界，同时只需要对整个设计空间中 20% 的设计点运行 HLS 流。实验结果表明，HL-Pow 可以实现精确的功率建模，与板载功率测量仅相差 4.67% (24.02 mW)。为了进一步促进面向功耗的优化，我们描述了一种建立在 HL-Pow 之上的新颖设计空间探索 (DSE) 算法，以在延迟和功耗之间进行权衡。该算法可以非常接近真实的帕累托边界，同时只需要对整个设计空间中 20% 的设计点运行 HLS 流。