This article presents a 14-bit 200-Ms/s pipelined analog-to-digital converter (ADC) for wide input frequency range. The ADC adopts a sample-and-hold amplifier-less (SHA-less) 3.5-bit front-end stage. A dedicated path combining architecture is proposed for the flash sub-ADC-based pipeline ADC to reduce the aperture error, and expand the ADC input frequency up to 490 MHz under 200-Ms/s sampling rate. To further improve the accuracy and reduce power, the sampling capacitor splitting and comparator interpolation techniques are used in the first stage. The proposed ADC has been designed and fabricated in a 180-nm CMOS technology with an area of 2.43 mm2 including ADC core, the biasing, and the calibration circuit. The measured signal to noise and distortion ratio (SNDR) is 70.6 and 65.6 dB for 30- and 385-MHz inputs, respectively. The SNDR remains 63.1 dB for 490-MHz input. The ADC core consumes 112-mW power under 1.8-V supply. The measured effective resolution bandwidth (ERBW) is about 250 MHz, and the Walden figure of merit (FoM) defined at the ERBW is 116 fJ/conversion-step.

中文翻译：

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具有孔径误差减少功能的 14 位 200Ms/s 无 SHA 流水线 ADC

本文介绍了一种用于宽输入频率范围的 14 位 200-Ms/s 流水线模数转换器 (ADC)。ADC 采用无采样保持放大器 (SHA-less) 3.5 位前端级。针对基于闪存子ADC的流水线ADC，提出了一种专用的路径组合架构，以减少孔径误差，并在200-Ms/s采样率下将ADC输入频率扩展到490 MHz。为了进一步提高精度和降低功耗，第一阶段采用了采样电容分路和比较器插值技术。所提议的 ADC 采用 180 nm CMOS 技术设计和制造，面积为 2.43 mm2，包括 ADC 内核、偏置和校准电路。对于 30-MHz 和 385-MHz 输入，测得的信噪比和失真比 (SNDR) 分别为 70.6 和 65.6 dB。SNDR 仍为 63。对于 490 MHz 输入为 1 dB。ADC 内核在 1.8V 电源下消耗 112mW 功率。测得的有效分辨率带宽 (ERBW) 约为 250 MHz，在 ERBW 处定义的瓦尔登品质因数 (FoM) 为 116 fJ/转换步长。