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A 90-nm 640 MHz 2 × VDD Output Buffer With 41.5% Slew Rate Improvement Using PVT Compensation
IEEE Transactions on Circuits and Systems II: Express Briefs ( IF 4.4 ) Pub Date : 2020-09-01 , DOI: 10.1109/tcsii.2020.3012150
Jian-An Wang , Yuan-Yao Zhao , Zheng-Ping Zhang

This brief presents a 2 $\times $ VDD output buffer using the encoded compensation technique to minimize slew rate (SR) deviation caused by PVT (process, voltage, temperature) variations. The process detectors can both detect all five process corners and ensure the compensation code unchanged in VT variations. Besides, the charging paths of the proposed voltage level converter (VLC) are independent and directly driven by logic gate, which applied in output stage to speed output buffer data rate up. The proposed design is implemented using a typical 90 nm 1.2 V 1P9M CMOS process, where the core area of a single output buffer is $400\,\,\mu \text{m}\times 56\,\,\mu \text{m}$ . The measured maximum data rate is 640/480 MHz given 1.2/2.5 V supply voltage, and the power consumption is 32.2 mW at 640 MHz data rate. the slew rate variation improvement is 41.5%/41.9% by PVT detection and SR compensation for VDDIO=1.2/2.5 V, respectively.

中文翻译:

90-nm 640 MHz 2 × VDD 输出缓冲器,使用 PVT 补偿将压摆率提高 41.5%

本简报介绍了 2 $\times $ VDD 输出缓冲器使用编码补偿技术来最小化由 PVT(工艺、电压、温度)变化引起的压摆率 (SR) 偏差。工艺检测器既可以检测所有五个工艺角,又可以确保补偿代码在 VT 变化中保持不变。此外,所提出的电压电平转换器(VLC)的充电路径是独立的,由逻辑门直接驱动,应用于输出级以加快输出缓冲器数据速率。所提议的设计是使用典型的 90 nm 1.2 V 1P9M CMOS 工艺实现的,其中单个输出缓冲器的核心面积为 $400\,\,\mu \text{m}\times 56\,\,\mu \text{m}$ . 在 1.2/2.5 V 电源电压下测得的最大数据速率为 640/480 MHz,640 MHz 数据速率下的功耗为 32.2 mW。VDDIO=1.2/2.5 V 时,PVT 检测和 SR 补偿的压摆率变化改进分别为 41.5%/41.9%。
更新日期:2020-09-01
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