In this brief, we present a tunable bandpass RF Sigma-Delta modulator with a fixed set of feedback DAC coefficients. The sampling frequency, $f_{s}$ , is tuned with the center frequency, $f_{0}$ , in order to maintain a fixed normalized center frequency, $f_{0}/f_{s}$ . Any variation in the loop delay is compensated to maintain a fixed normalized loop-delay $t_{d}/T_{s}$ . The bandpass Sigma-Delta, reported in this brief, is based on an LC resonator with tunable center frequency from 1.5 to 3.0 GHz and a corresponding sampling frequency from 6.0 to 12.0 GHz. For an oversampling ratio of 64, the ADC achieves the same SNDR of 37 dB and the same Dynamic Range of 45 dB over the complete tuning range. This performance is achieved for a bandwith of 47 MHz at 1.5GHz and a Bandwidth of 93 MHz at 3 GHz. The ADC, fabricated in a 65 nm CMOS process, consumes only 13 mW from a 1.2 V supply. In order to compare this circuit with the state of the art, we use not only the conventional ADC Figure of Merit but we also use a Figure of Merit dedicated to RF circuits. In this case, the measured chip center frequency, noise figure and non-linearity are also taken into account in the comparison.

中文翻译：

---

具有一组固定系数和可编程环路延迟的 1.5 至 3.0GHz 可调谐 RF ΣΔ ADC

在本简报中，我们展示了一个具有一组固定反馈 DAC 系数的可调带通 RF Sigma-Delta 调制器。采样频率， $f_{s}$ ，与中心频率调谐， $f_{0}$ ，为了保持固定的归一化中心频率， $f_{0}/f_{s}$ . 环路延迟的任何变化都会得到补偿，以保持固定的归一化环路延迟 $t_{d}/T_{s}$ . 本简报中报告的带通 Sigma-Delta 基于 LC 谐振器，其可调中心频率为 1.5 至 3.0 GHz，相应的采样频率为 6.0 至 12.0 GHz。对于 64 的过采样率，ADC 在整个调谐范围内实现相同的 37 dB SNDR 和相同的 45 dB 动态范围。这种性能是在 1.5GHz 时的 47 MHz 带宽和 3 GHz 时的 93 MHz 带宽下实现的。ADC 采用 65 nm CMOS 工艺制造，在 1.2 V 电源下仅消耗 13 mW。为了将该电路与现有技术进行比较，我们不仅使用传统的 ADC 品质因数，而且还使用专用于 RF 电路的品质因数。在这种情况下，在比较中还考虑了测量的芯片中心频率、噪声系数和非线性度。